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https://github.com/AsahiLinux/u-boot
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174d728471
Update my and DPs email address to match current setup. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/aba5b19b9c5a95608829e86ad5cc4671c940f1bb.1688992543.git.michal.simek@amd.com
56 lines
1.2 KiB
C
56 lines
1.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2013 - 2014 Xilinx, Inc
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*
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* Michal Simek <michal.simek@amd.com>
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*/
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#include <common.h>
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#include <command.h>
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#include <image.h>
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#include <log.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/u-boot.h>
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#include <linux/stringify.h>
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void board_boot_order(u32 *spl_boot_list)
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{
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spl_boot_list[0] = BOOT_DEVICE_NOR;
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spl_boot_list[1] = BOOT_DEVICE_RAM;
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spl_boot_list[2] = BOOT_DEVICE_SPI;
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}
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/* Board initialization after bss clearance */
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void spl_board_init(void)
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{
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/* enable console uart printing */
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preloader_console_init();
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}
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#ifdef CONFIG_SPL_OS_BOOT
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void __noreturn jump_to_image_linux(struct spl_image_info *spl_image)
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{
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debug("Entering kernel arg pointer: 0x%p\n", spl_image->arg);
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typedef void (*image_entry_arg_t)(char *, ulong, ulong)
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__attribute__ ((noreturn));
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image_entry_arg_t image_entry =
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(image_entry_arg_t)spl_image->entry_point;
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image_entry(NULL, 0, (ulong)spl_image->arg);
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}
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int spl_start_uboot(void)
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{
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return 0;
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}
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#endif /* CONFIG_SPL_OS_BOOT */
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int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
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{
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__asm__ __volatile__ (
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"mts rmsr, r0;" \
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"brai " __stringify(CONFIG_XILINX_MICROBLAZE0_VECTOR_BASE_ADDR));
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return 0;
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}
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