mirror of
https://github.com/AsahiLinux/u-boot
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b6afa7cf62
This driver is actually used for powerpc and m68k/ColdFire. On ColdFire SoC's, interrupt flag get not set if IIEN flag (mbcr bit6, interrupt enabled) is not set appropriately before each transfert. As a result, the transfert hangs forever waiting for IIEN. This patch set IIEN before each transfert, while considering this fix as not harming powerpc arch. Signed-off-by: Angelo Dureghello <angelo@kernel-space.org>
70 lines
1.5 KiB
C
70 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Freescale I2C Controller
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*
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* Copyright 2006 Freescale Semiconductor, Inc.
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*
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* Based on earlier versions by Gleb Natapov <gnatapov@mrv.com>,
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* Xianghua Xiao <x.xiao@motorola.com>, Eran Liberty (liberty@freescale.com),
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* and Jeff Brown.
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* Some bits are taken from linux driver writen by adrian@humboldt.co.uk.
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*/
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#ifndef _ASM_FSL_I2C_H_
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#define _ASM_FSL_I2C_H_
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#include <asm/types.h>
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typedef struct fsl_i2c_base {
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u8 adr; /* I2C slave address */
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u8 res0[3];
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#define I2C_ADR 0xFE
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#define I2C_ADR_SHIFT 1
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#define I2C_ADR_RES ~(I2C_ADR)
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u8 fdr; /* I2C frequency divider register */
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u8 res1[3];
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#define IC2_FDR 0x3F
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#define IC2_FDR_SHIFT 0
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#define IC2_FDR_RES ~(IC2_FDR)
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u8 cr; /* I2C control redister */
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u8 res2[3];
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#define I2C_CR_MEN 0x80
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#define I2C_CR_MIEN 0x40
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#define I2C_CR_MSTA 0x20
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#define I2C_CR_MTX 0x10
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#define I2C_CR_TXAK 0x08
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#define I2C_CR_RSTA 0x04
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#define I2C_CR_BCST 0x01
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u8 sr; /* I2C status register */
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u8 res3[3];
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#define I2C_SR_MCF 0x80
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#define I2C_SR_MAAS 0x40
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#define I2C_SR_MBB 0x20
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#define I2C_SR_MAL 0x10
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#define I2C_SR_BCSTM 0x08
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#define I2C_SR_SRW 0x04
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#define I2C_SR_MIF 0x02
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#define I2C_SR_RXAK 0x01
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u8 dr; /* I2C data register */
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u8 res4[3];
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#define I2C_DR 0xFF
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#define I2C_DR_SHIFT 0
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#define I2C_DR_RES ~(I2C_DR)
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} fsl_i2c_t;
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#if CONFIG_IS_ENABLED(DM_I2C)
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struct fsl_i2c_dev {
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struct fsl_i2c_base __iomem *base; /* register base */
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u32 i2c_clk;
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u32 index;
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u8 slaveadd;
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uint speed;
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};
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#endif
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#endif /* _ASM_I2C_H_ */
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