u-boot/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts
James Byrne 83f71ef558 net: phy: micrel: Use correct skew values on KSZ9021
Commit ff7bd212cb ("net: phy: micrel: fix divisor value for KSZ9031
phy skew") fixed the skew value divisor for the KSZ9031, but left the
code using the same divisor for the KSZ9021, which is incorrect.

The preceding commit c16e69f702 ("net: phy: micrel: add documentation
for Micrel KSZ90x1 binding") added the DTS documentation for the
KSZ90x1, changing it from the equivalent file in the Linux kernel to
correctly state that for this part the skew value is set in 120ps steps,
whereas the Linux documentation and driver continue to this day to use
the incorrect value of 200 that came from the original KSZ9021 datasheet
before it was corrected in revision 1.2 (Feb 2014).

This commit sorts out the resulting confusion in a consistent way by
making the following changes:

- Update the documentation to be clear about what the skew values mean,
in the same was as for the KSZ9031.

- Update the Micrel PHY driver to select the appropriate divisor for
both parts.

- Adjust all the device trees that state skew values for KSZ9021 PHYs to
use values based on 120ps steps instead of 200ps steps. This will result
in the same values being programmed into the skew registers as the
equivalent device trees in the Linux kernel do, where it incorrectly
uses 200ps steps (since that's where all these device trees were copied
from).

Signed-off-by: James Byrne <james.byrne@origamienergy.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-05-08 17:27:01 -05:00

251 lines
4.2 KiB
Text

// SPDX-License-Identifier: (GPL-2.0+ OR X11)
/*
* Copyright (C) 2015 Marek Vasut <marex@denx.de>
*/
#include "socfpga_cyclone5.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "samtec VIN|ING FPGA";
compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga";
chosen {
bootargs = "earlyprintk";
stdout-path = "serial0:115200n8";
};
memory@0 {
name = "memory";
device_type = "memory";
reg = <0x0 0x40000000>; /* 1GB */
};
aliases {
/*
* This allow the ethaddr uboot environment variable contents
* to be added to the gmac1 device tree blob.
*/
ethernet0 = &gmac1;
ethernet1 = &gmac0;
};
gpio-keys {
compatible = "gpio-keys";
hps_temp0 {
label = "BTN_0"; /* TEMP_OS */
gpios = <&portc 18 GPIO_ACTIVE_LOW>; /* HPS_GPIO60 */
linux,code = <BTN_0>;
};
hps_hkey0 {
label = "BTN_1"; /* DIS_PWR */
gpios = <&portc 19 GPIO_ACTIVE_LOW>; /* HPS_GPIO61 */
linux,code = <BTN_1>;
};
hps_hkey1 {
label = "hps_hkey1"; /* POWER_DOWN */
gpios = <&portc 20 GPIO_ACTIVE_LOW>; /* HPS_GPIO62 */
linux,code = <KEY_POWER>;
};
};
regulator-usb-nrst {
compatible = "regulator-fixed";
regulator-name = "usb_nrst";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&portb 5 GPIO_ACTIVE_HIGH>;
startup-delay-us = <70000>;
enable-active-high;
regulator-always-on;
};
};
&gmac1 {
status = "okay";
phy-mode = "rgmii";
phy-handle = <&phy1>;
snps,reset-gpio = <&porta 0 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <10000 10000 10000>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy1: ethernet-phy@1 {
reg = <1>;
rxd0-skew-ps = <0>;
rxd1-skew-ps = <0>;
rxd2-skew-ps = <0>;
rxd3-skew-ps = <0>;
txen-skew-ps = <0>;
txc-skew-ps = <1560>;
rxdv-skew-ps = <0>;
rxc-skew-ps = <1200>;
};
};
};
&gpio0 { /* GPIO 0..29 */
status = "okay";
};
&gpio1 { /* GPIO 30..57 */
status = "okay";
};
&gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */
status = "okay";
};
&i2c0 {
status = "okay";
gpio: pca9557@1f {
compatible = "nxp,pca9557";
reg = <0x1f>;
gpio-controller;
#gpio-cells = <2>;
};
temp: lm75@48 {
compatible = "lm75";
reg = <0x48>;
};
at24@50 {
compatible = "atmel,24c01";
pagesize = <8>;
reg = <0x50>;
};
i2cswitch@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
i2c@6 { /* Backplane EEPROM */
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
eeprom@51 {
compatible = "atmel,24c01";
pagesize = <8>;
reg = <0x51>;
};
};
i2c@7 { /* Power board EEPROM */
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
eeprom@51 {
compatible = "atmel,24c01";
pagesize = <8>;
reg = <0x51>;
};
};
};
};
&i2c1 {
status = "okay";
clock-frequency = <100000>;
at24@50 {
compatible = "atmel,24c02";
pagesize = <8>;
reg = <0x50>;
};
};
&qspi {
status = "okay";
n25q128@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128";
reg = <0>; /* chip select */
spi-max-frequency = <100000000>;
m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
};
n25q00@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q00";
reg = <1>; /* chip select */
spi-max-frequency = <100000000>;
m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
};
};
&usb0 {
dr_mode = "host";
status = "okay";
};
&usb1 {
dr_mode = "peripheral";
status = "okay";
};