mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-05 20:54:31 +00:00
8ec42856f1
One ls2080a, there is one SATA 3.0 advanced host controller interface which is a high-performance SATA solution that delivers comprehensive and fully-compliant generation 3 (1.5 Gb/s - 6.0 Gb/s) serial ATA capabilities, in accordance with the serial ATA revision 3.0 of Serial ATA International Organization. Add sata node to support this feature. Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
167 lines
5 KiB
Text
167 lines
5 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
|
/*
|
|
* Freescale ls2080a SOC common device tree source
|
|
*
|
|
* Copyright 2013-2015 Freescale Semiconductor, Inc.
|
|
*/
|
|
|
|
/ {
|
|
compatible = "fsl,ls2080a";
|
|
interrupt-parent = <&gic>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
|
|
memory@80000000 {
|
|
device_type = "memory";
|
|
reg = <0x00000000 0x80000000 0 0x80000000>;
|
|
/* DRAM space - 1, size : 2 GB DRAM */
|
|
};
|
|
|
|
gic: interrupt-controller@6000000 {
|
|
compatible = "arm,gic-v3";
|
|
reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
|
|
<0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
|
|
#interrupt-cells = <3>;
|
|
interrupt-controller;
|
|
interrupts = <1 9 0x4>;
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
|
|
<1 14 0x8>, /* Physical Non-Secure PPI, active-low */
|
|
<1 11 0x8>, /* Virtual PPI, active-low */
|
|
<1 10 0x8>; /* Hypervisor PPI, active-low */
|
|
};
|
|
|
|
serial0: serial@21c0500 {
|
|
device_type = "serial";
|
|
compatible = "fsl,ns16550", "ns16550a";
|
|
reg = <0x0 0x21c0500 0x0 0x100>;
|
|
clock-frequency = <0>; /* Updated by bootloader */
|
|
interrupts = <0 32 0x1>; /* edge triggered */
|
|
};
|
|
|
|
serial1: serial@21c0600 {
|
|
device_type = "serial";
|
|
compatible = "fsl,ns16550", "ns16550a";
|
|
reg = <0x0 0x21c0600 0x0 0x100>;
|
|
clock-frequency = <0>; /* Updated by bootloader */
|
|
interrupts = <0 32 0x1>; /* edge triggered */
|
|
};
|
|
|
|
fsl_mc: fsl-mc@80c000000 {
|
|
compatible = "fsl,qoriq-mc";
|
|
reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
|
|
<0x00000000 0x08340000 0 0x40000>; /* MC control reg */
|
|
};
|
|
|
|
dspi: dspi@2100000 {
|
|
compatible = "fsl,vf610-dspi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x0 0x2100000 0x0 0x10000>;
|
|
interrupts = <0 26 0x4>; /* Level high type */
|
|
num-cs = <6>;
|
|
};
|
|
|
|
qspi: quadspi@1550000 {
|
|
compatible = "fsl,vf610-qspi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x0 0x20c0000 0x0 0x10000>,
|
|
<0x0 0x20000000 0x0 0x10000000>;
|
|
reg-names = "QuadSPI", "QuadSPI-memory";
|
|
num-cs = <4>;
|
|
};
|
|
|
|
esdhc: esdhc@0 {
|
|
compatible = "fsl,esdhc";
|
|
reg = <0x0 0x2140000 0x0 0x10000>;
|
|
interrupts = <0 28 0x4>; /* Level high type */
|
|
little-endian;
|
|
bus-width = <4>;
|
|
};
|
|
|
|
usb0: usb3@3100000 {
|
|
compatible = "fsl,layerscape-dwc3";
|
|
reg = <0x0 0x3100000 0x0 0x10000>;
|
|
interrupts = <0 80 0x4>; /* Level high type */
|
|
dr_mode = "host";
|
|
};
|
|
|
|
usb1: usb3@3110000 {
|
|
compatible = "fsl,layerscape-dwc3";
|
|
reg = <0x0 0x3110000 0x0 0x10000>;
|
|
interrupts = <0 81 0x4>; /* Level high type */
|
|
dr_mode = "host";
|
|
};
|
|
|
|
pcie@3400000 {
|
|
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
|
reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
|
|
0x00 0x03480000 0x0 0x80000 /* lut registers */
|
|
0x10 0x00000000 0x0 0x20000>; /* configuration space */
|
|
reg-names = "dbi", "lut", "config";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
num-lanes = <4>;
|
|
bus-range = <0x0 0xff>;
|
|
ranges = <0x81000000 0x0 0x00000000 0x10 0x00020000 0x0 0x00010000 /* downstream I/O */
|
|
0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
|
};
|
|
|
|
pcie@3500000 {
|
|
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
|
reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
|
|
0x00 0x03580000 0x0 0x80000 /* lut registers */
|
|
0x12 0x00000000 0x0 0x20000>; /* configuration space */
|
|
reg-names = "dbi", "lut", "config";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
num-lanes = <4>;
|
|
bus-range = <0x0 0xff>;
|
|
ranges = <0x81000000 0x0 0x00000000 0x12 0x00020000 0x0 0x00010000 /* downstream I/O */
|
|
0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
|
};
|
|
|
|
pcie@3600000 {
|
|
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
|
reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
|
|
0x00 0x03680000 0x0 0x80000 /* lut registers */
|
|
0x14 0x00000000 0x0 0x20000>; /* configuration space */
|
|
reg-names = "dbi", "lut", "config";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
num-lanes = <8>;
|
|
bus-range = <0x0 0xff>;
|
|
ranges = <0x81000000 0x0 0x00000000 0x14 0x00020000 0x0 0x00010000 /* downstream I/O */
|
|
0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
|
};
|
|
|
|
pcie@3700000 {
|
|
compatible = "fsl,ls-pcie", "snps,dw-pcie";
|
|
reg = <0x00 0x03700000 0x0 0x80000 /* dbi registers */
|
|
0x00 0x03780000 0x0 0x80000 /* lut registers */
|
|
0x16 0x00000000 0x0 0x20000>; /* configuration space */
|
|
reg-names = "dbi", "lut", "config";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
num-lanes = <4>;
|
|
bus-range = <0x0 0xff>;
|
|
ranges = <0x81000000 0x0 0x00000000 0x16 0x00020000 0x0 0x00010000 /* downstream I/O */
|
|
0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
|
};
|
|
|
|
sata: sata@3200000 {
|
|
compatible = "fsl,ls2080a-ahci";
|
|
reg = <0x0 0x3200000 0x0 0x10000>;
|
|
interrupts = <0 133 0x4>; /* Level high type */
|
|
status = "disabled";
|
|
};
|
|
|
|
};
|