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ac80ac09c8
Avnet UltraZed-EV Starter Kit is composed by the UltraZed-EV SoM and the
only publicly-available compatible carrier card. The SoM is based on the EV
version of the Xilinx ZynqMP SoC+FPGA.
The psu_init_gpl.c file has been generated from the board definition files
at [0] using Vivado 2018.3 and then minimized by
tools/zynqmp_psu_init_minimize.sh. Manually removed serdes init code since
it is not mentioned in device tree and fixed a checkpatch error.
[0] 3686c9ff7d/ultrazed_7ev_cc/1.1
Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
56 lines
1 KiB
Text
56 lines
1 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* UltraZed-EV SoM v1
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* http://ultrazed.org/product/ultrazed-ev
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*/
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/dts-v1/;
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#include "zynqmp.dtsi"
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#include "zynqmp-clk-ccf.dtsi"
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/ {
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model = "Avnet UltraZed EV SoM v1.0";
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compatible = "avnet,ultrazedev-som-v1.0", "xlnx,zynqmp";
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memory {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>, /* 2 GB @ offset 0 */
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<0x8 0x0 0x0 0x80000000>; /* 2 GB @ offset 32GB */
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};
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};
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&i2c1 {
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clock-frequency = <400000>;
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status = "okay";
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i2cswitch@70 {
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compatible = "nxp,pca9543";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x70>;
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/* I2C connected to Carrier Card via JX3A1/JX3C1 */
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i2c_cc: i2c@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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/* Marvell 88E1512-A0-NNP2I000 Ethernet PHY */
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&gem3 {
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phy-mode = "rgmii-id";
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phy-handle = <&gem3phy>;
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gem3phy: ethernet-phy@0 {
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reg = <0>;
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};
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};
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/* Micron MTFC8GAKAJCN-4M 8 GB eMMC */
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&sdhci0 {
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status = "okay";
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xlnx,mio_bank = <0>;
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clock-frequency = <199998000>;
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};
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