mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-05 20:54:31 +00:00
825dd50f59
When armada-385.dtsi was sync'd from Linux the name of the node describing the pcie controller was changed from pcie-controller to pcie. Some of the boards that include armada-385.dtsi were missed in the update retaining the old name. This updates the affected boards. Reported-by: Влад Мао <vlaomao@gmail.com> Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
375 lines
8.8 KiB
Text
375 lines
8.8 KiB
Text
/*
|
|
* Device Tree file for SolidRun Clearfog revision A1 rev 2.0 (88F6828)
|
|
*
|
|
* Copyright (C) 2015 Russell King
|
|
*
|
|
* This board is in development; the contents of this file work with
|
|
* the A1 rev 2.0 of the board, which does not represent final
|
|
* production board. Things will change, don't expect this file to
|
|
* remain compatible info the future.
|
|
*
|
|
* This file is dual-licensed: you can use it either under the terms
|
|
* of the GPL or the X11 license, at your option. Note that this dual
|
|
* licensing only applies to this file, and not this project as a
|
|
* whole.
|
|
*
|
|
* a) This file is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License
|
|
* version 2 as published by the Free Software Foundation.
|
|
*
|
|
* This file is distributed in the hope that it will be useful
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* Or, alternatively
|
|
*
|
|
* b) Permission is hereby granted, free of charge, to any person
|
|
* obtaining a copy of this software and associated documentation
|
|
* files (the "Software"), to deal in the Software without
|
|
* restriction, including without limitation the rights to use
|
|
* copy, modify, merge, publish, distribute, sublicense, and/or
|
|
* sell copies of the Software, and to permit persons to whom the
|
|
* Software is furnished to do so, subject to the following
|
|
* conditions:
|
|
*
|
|
* The above copyright notice and this permission notice shall be
|
|
* included in all copies or substantial portions of the Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
|
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
|
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
|
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
|
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
|
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
|
* OTHER DEALINGS IN THE SOFTWARE.
|
|
*/
|
|
|
|
/dts-v1/;
|
|
#include <dt-bindings/input/input.h>
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
#include "armada-388.dtsi"
|
|
#include "armada-38x-solidrun-microsom.dtsi"
|
|
|
|
/ {
|
|
model = "SolidRun Clearfog A1";
|
|
compatible = "solidrun,clearfog-a1", "marvell,armada388",
|
|
"marvell,armada385", "marvell,armada380";
|
|
|
|
aliases {
|
|
/* So that mvebu u-boot can update the MAC addresses */
|
|
ethernet1 = ð0;
|
|
ethernet2 = ð1;
|
|
ethernet3 = ð2;
|
|
spi1 = &spi1;
|
|
i2c0 = &i2c0;
|
|
i2c1 = &i2c1;
|
|
};
|
|
|
|
chosen {
|
|
stdout-path = "serial0:115200n8";
|
|
};
|
|
|
|
reg_3p3v: regulator-3p3v {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "3P3V";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
soc {
|
|
internal-regs {
|
|
rtc@a3800 {
|
|
/*
|
|
* If the rtc doesn't work, run "date reset"
|
|
* twice in u-boot.
|
|
*/
|
|
status = "okay";
|
|
};
|
|
|
|
sata@a8000 {
|
|
/* pinctrl? */
|
|
status = "okay";
|
|
};
|
|
|
|
sata@e0000 {
|
|
/* pinctrl? */
|
|
status = "okay";
|
|
};
|
|
|
|
sdhci@d8000 {
|
|
bus-width = <4>;
|
|
cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
|
|
no-1-8-v;
|
|
pinctrl-0 = <µsom_sdhci_pins
|
|
&clearfog_sdhci_cd_pins>;
|
|
pinctrl-names = "default";
|
|
status = "okay";
|
|
vmmc = <®_3p3v>;
|
|
wp-inverted;
|
|
};
|
|
|
|
serial@12100 {
|
|
/* mikrobus uart */
|
|
pinctrl-0 = <&mikro_uart_pins>;
|
|
pinctrl-names = "default";
|
|
status = "okay";
|
|
};
|
|
|
|
usb3@f8000 {
|
|
/* CON7, USB-A port on back of device */
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
pcie {
|
|
status = "okay";
|
|
/*
|
|
* The two PCIe units are accessible through
|
|
* the mini-PCIe connectors on the board.
|
|
*/
|
|
pcie@2,0 {
|
|
/* Port 1, Lane 0. CONN3, nearest power. */
|
|
reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
|
|
status = "okay";
|
|
};
|
|
pcie@3,0 {
|
|
/* Port 2, Lane 0. CONN2, nearest CPU. */
|
|
reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
};
|
|
|
|
gpio-keys {
|
|
compatible = "gpio-keys";
|
|
pinctrl-0 = <&rear_button_pins>;
|
|
pinctrl-names = "default";
|
|
|
|
button_0 {
|
|
/* The rear SW3 button */
|
|
label = "Rear Button";
|
|
gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
|
|
linux,can-disable;
|
|
linux,code = <BTN_0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&w25q32 {
|
|
status = "okay";
|
|
};
|
|
|
|
ð1 {
|
|
managed = "in-band-status";
|
|
phy-mode = "sgmii";
|
|
status = "okay";
|
|
};
|
|
|
|
ð2 {
|
|
phy-mode = "sgmii";
|
|
status = "okay";
|
|
};
|
|
|
|
&i2c0 {
|
|
clock-frequency = <400000>;
|
|
pinctrl-0 = <&i2c0_pins>;
|
|
pinctrl-names = "default";
|
|
status = "okay";
|
|
|
|
/*
|
|
* PCA9655 GPIO expander, up to 1MHz clock.
|
|
* 0-CON3 CLKREQ#
|
|
* 1-CON3 PERST#
|
|
* 2-CON2 PERST#
|
|
* 3-CON3 W_DISABLE
|
|
* 4-CON2 CLKREQ#
|
|
* 5-USB3 overcurrent
|
|
* 6-USB3 power
|
|
* 7-CON2 W_DISABLE
|
|
* 8-JP4 P1
|
|
* 9-JP4 P4
|
|
* 10-JP4 P5
|
|
* 11-m.2 DEVSLP
|
|
* 12-SFP_LOS
|
|
* 13-SFP_TX_FAULT
|
|
* 14-SFP_TX_DISABLE
|
|
* 15-SFP_MOD_DEF0
|
|
*/
|
|
expander0: gpio-expander@20 {
|
|
/*
|
|
* This is how it should be:
|
|
* compatible = "onnn,pca9655",
|
|
* "nxp,pca9555";
|
|
* but you can't do this because of
|
|
* the way I2C works.
|
|
*/
|
|
compatible = "nxp,pca9555";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
reg = <0x20>;
|
|
|
|
pcie1_0_clkreq {
|
|
gpio-hog;
|
|
gpios = <0 GPIO_ACTIVE_LOW>;
|
|
input;
|
|
line-name = "pcie1.0-clkreq";
|
|
};
|
|
pcie1_0_w_disable {
|
|
gpio-hog;
|
|
gpios = <3 GPIO_ACTIVE_LOW>;
|
|
output-low;
|
|
line-name = "pcie1.0-w-disable";
|
|
};
|
|
pcie2_0_clkreq {
|
|
gpio-hog;
|
|
gpios = <4 GPIO_ACTIVE_LOW>;
|
|
input;
|
|
line-name = "pcie2.0-clkreq";
|
|
};
|
|
pcie2_0_w_disable {
|
|
gpio-hog;
|
|
gpios = <7 GPIO_ACTIVE_LOW>;
|
|
output-low;
|
|
line-name = "pcie2.0-w-disable";
|
|
};
|
|
usb3_ilimit {
|
|
gpio-hog;
|
|
gpios = <5 GPIO_ACTIVE_LOW>;
|
|
input;
|
|
line-name = "usb3-current-limit";
|
|
};
|
|
usb3_power {
|
|
gpio-hog;
|
|
gpios = <6 GPIO_ACTIVE_HIGH>;
|
|
output-high;
|
|
line-name = "usb3-power";
|
|
};
|
|
m2_devslp {
|
|
gpio-hog;
|
|
gpios = <11 GPIO_ACTIVE_HIGH>;
|
|
output-low;
|
|
line-name = "m.2 devslp";
|
|
};
|
|
};
|
|
|
|
mikrobus_adc: mcp3021@4c {
|
|
compatible = "microchip,mcp3021";
|
|
reg = <0x4c>;
|
|
};
|
|
};
|
|
|
|
&i2c1 {
|
|
/*
|
|
* Routed to SFP, mikrobus, and PCIe.
|
|
* SFP limits this to 100kHz, and requires
|
|
* an AT24C01A/02/04 with address pins tied
|
|
* low, which takes addresses 0x50 and 0x51.
|
|
* Mikrobus doesn't specify beyond an I2C
|
|
* bus being present.
|
|
* PCIe uses ARP to assign addresses, or
|
|
* 0x63-0x64.
|
|
*/
|
|
clock-frequency = <100000>;
|
|
pinctrl-0 = <&clearfog_i2c1_pins>;
|
|
pinctrl-names = "default";
|
|
status = "okay";
|
|
};
|
|
|
|
&pinctrl {
|
|
clearfog_i2c1_pins: i2c1-pins {
|
|
/* SFP, PCIe, mSATA, mikrobus */
|
|
marvell,pins = "mpp26", "mpp27";
|
|
marvell,function = "i2c1";
|
|
};
|
|
clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
|
|
marvell,pins = "mpp20";
|
|
marvell,function = "gpio";
|
|
};
|
|
clearfog_spi1_cs_pins: spi1-cs-pins {
|
|
marvell,pins = "mpp55";
|
|
marvell,function = "spi1";
|
|
};
|
|
mikro_pins: mikro-pins {
|
|
/* int: mpp22 rst: mpp29 */
|
|
marvell,pins = "mpp22", "mpp29";
|
|
marvell,function = "gpio";
|
|
};
|
|
mikro_spi_pins: mikro-spi-pins {
|
|
marvell,pins = "mpp43";
|
|
marvell,function = "spi1";
|
|
};
|
|
mikro_uart_pins: mikro-uart-pins {
|
|
marvell,pins = "mpp24", "mpp25";
|
|
marvell,function = "ua1";
|
|
};
|
|
rear_button_pins: rear-button-pins {
|
|
marvell,pins = "mpp34";
|
|
marvell,function = "gpio";
|
|
};
|
|
};
|
|
|
|
&spi1 {
|
|
/*
|
|
* Add SPI CS pins for clearfog:
|
|
* CS0: W25Q32
|
|
* CS1:
|
|
* CS2: mikrobus
|
|
*/
|
|
pinctrl-0 = <&spi1_pins &mikro_spi_pins>;
|
|
pinctrl-names = "default";
|
|
status = "okay";
|
|
};
|
|
|
|
/*
|
|
+#define A38x_CUSTOMER_BOARD_1_MPP16_23 0x00400011
|
|
MPP18: gpio ? (pca9655 int?)
|
|
MPP19: gpio ? (clkreq?)
|
|
MPP20: gpio ? (sd0 detect)
|
|
MPP21: sd0:cmd x sd0
|
|
MPP22: gpio x mikro int
|
|
MPP23: gpio x switch irq
|
|
+#define A38x_CUSTOMER_BOARD_1_MPP24_31 0x22043333
|
|
MPP24: ua1:rxd x mikro rx
|
|
MPP25: ua1:txd x mikro tx
|
|
MPP26: i2c1:sck x mikro sck
|
|
MPP27: i2c1:sda x mikro sda
|
|
MPP28: sd0:clk x sd0
|
|
MPP29: gpio x mikro rst
|
|
MPP30: ge1:txd2 ? (config)
|
|
MPP31: ge1:txd3 ? (config)
|
|
+#define A38x_CUSTOMER_BOARD_1_MPP32_39 0x44400002
|
|
MPP32: ge1:txctl ? (unused)
|
|
MPP33: gpio ? (pic_com0)
|
|
MPP34: gpio x rear button (pic_com1)
|
|
MPP35: gpio ? (pic_com2)
|
|
MPP36: gpio ? (unused)
|
|
MPP37: sd0:d3 x sd0
|
|
MPP38: sd0:d0 x sd0
|
|
MPP39: sd0:d1 x sd0
|
|
+#define A38x_CUSTOMER_BOARD_1_MPP40_47 0x41144004
|
|
MPP40: sd0:d2 x sd0
|
|
MPP41: gpio x switch reset
|
|
MPP42: gpio ? sw1-1
|
|
MPP43: spi1:cs2 x mikro cs
|
|
MPP44: sata3:prsnt ? (unused)
|
|
MPP45: ref:clk_out0 ?
|
|
MPP46: ref:clk_out1 x switch clk
|
|
MPP47: 4 ? (unused)
|
|
+#define A38x_CUSTOMER_BOARD_1_MPP48_55 0x40333333
|
|
MPP48: tdm:pclk
|
|
MPP49: tdm:fsync
|
|
MPP50: tdm:drx
|
|
MPP51: tdm:dtx
|
|
MPP52: tdm:int
|
|
MPP53: tdm:rst
|
|
MPP54: gpio ? (pwm)
|
|
MPP55: spi1:cs1 x slic
|
|
+#define A38x_CUSTOMER_BOARD_1_MPP56_63 0x00004444
|
|
MPP56: spi1:mosi x mikro mosi
|
|
MPP57: spi1:sck x mikro sck
|
|
MPP58: spi1:miso x mikro miso
|
|
MPP59: spi1:cs0 x w25q32
|
|
*/
|