mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
b75d8dc564
The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> |
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| .. | ||
| ddr.c | ||
| eth.c | ||
| Kconfig | ||
| ls1046afrwy.c | ||
| MAINTAINERS | ||
| Makefile | ||
| README | ||
Overview
--------
The LS1046A Freeway Board (iFRWY) is a high-performance computing,
evaluation, and development platform that supports the QorIQ LS1046A
LayerScape Architecture processor. The FRWY-LS1046A provides SW development
platform for the Freescale LS1046A processor series, with a complete
debugging environment. The FRWY-LS1046A is lead-free and RoHS-compliant.
LS1046A SoC Overview
--------------------
Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A
SoC overview.
FRWY-LS1046A board Overview
-----------------------
- SERDES1 Connections, 4 lanes supporting:
- Lane0: Unused
- Lane1: Unused
- Lane2: QSGMII
- Lane3: Unused
- SERDES2 Connections, 4 lanes supporting:
- Lane0: Unused
- Lane1: PCIe3 with PCIe x1 slot
- Lane2: Unused
- Lane3: PCIe3 with PCIe x1 slot
- DDR Controller
- 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s
-IFC/Local Bus
- One 512 MB NAND flash with ECC support
- USB 3.0
- Two Type A port
- SDHC: connects directly to a full microSD slot
- QSPI: 64 MB high-speed flash Memory for boot code and storage
- 4 I2C controllers
- UART
- Two 4-pin serial ports at up to 115.2 Kbit/s
- Two DB9 D-Type connectors supporting one Serial port each
- ARM JTAG support
Memory map from core's view
----------------------------
Start Address End Address Description Size
0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB
0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB
0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB
0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB
0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB
0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB
0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - CPLD 4KB
0x00_8000_0000 - 0x00_FFFF_FFFF DRAM1 2GB
0x05_0000_0000 - 0x05_07FF_FFFF QMAN S/W Portal 128M
0x05_0800_0000 - 0x05_0FFF_FFFF BMAN S/W Portal 128M
0x08_8000_0000 - 0x09_FFFF_FFFF DRAM2 6GB
0x40_0000_0000 - 0x47_FFFF_FFFF PCI Express1 32G
0x48_0000_0000 - 0x4F_FFFF_FFFF PCI Express2 32G
0x50_0000_0000 - 0x57_FFFF_FFFF PCI Express3 32G
QSPI flash map:
Start Address End Address Description Size
0x00_4000_0000 - 0x00_400F_FFFF RCW + PBI + BL2 1MB
0x00_4010_0000 - 0x00_404F_FFFF FIP Image
(Bl31 + BL32(optee.
bin) + Bl33(uboot)
+ headers for secure
boot) 4MB
0x00_4050_0000 - 0x00_405F_FFFF Boot Firmware Env 1MB
0x00_4060_0000 - 0x00_408F_FFFF Secure boot headers 3MB
0x00_4090_0000 - 0x00_4093_FFFF FMan ucode 256KB
0x00_4094_0000 - 0x00_4097_FFFF QE/uQE firmware 256KB
0x00_409C_0000 - 0x00_409F_FFFF Reserved 256KB
0x00_4100_0000 - 0x00_43FF_FFFF FIT Image 48MB
Booting Options
---------------
a) QSPI boot
b) microSD boot