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https://github.com/AsahiLinux/u-boot
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8ad92118dc
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
103 lines
1.9 KiB
C
103 lines
1.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2004,2009-2011 Freescale Semiconductor, Inc.
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* Jeff Brown
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* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
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*/
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/*
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* cpu_init.c - low level cpu init
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <common.h>
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#include <init.h>
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#include <mpc86xx.h>
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#include <asm/mmu.h>
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#include <asm/fsl_law.h>
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#include <asm/fsl_serdes.h>
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#include <asm/mp.h>
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extern void srio_init(void);
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Breathe some life into the CPU...
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*
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* Set up the memory map
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* initialize a bunch of registers
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*/
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void cpu_init_f(void)
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{
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/* Pointer is writable since we allocated a register for it */
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gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
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/* Clear initial global data */
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memset ((void *) gd, 0, sizeof (gd_t));
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#ifdef CONFIG_FSL_LAW
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init_laws();
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#endif
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setup_bats();
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init_early_memctl_regs();
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#if defined(CONFIG_FSL_DMA)
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dma_init();
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#endif
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/* enable the timebase bit in HID0 */
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set_hid0(get_hid0() | 0x4000000);
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/* enable EMCP, SYNCBE | ABE bits in HID1 */
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set_hid1(get_hid1() | 0x80000C00);
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}
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/*
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* initialize higher level parts of CPU like timers
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*/
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int cpu_init_r(void)
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{
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/* needs to be in ram since code uses global static vars */
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fsl_serdes_init();
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#ifdef CONFIG_SYS_SRIO
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srio_init();
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#endif
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#if defined(CONFIG_MP)
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setup_mp();
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#endif
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return 0;
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}
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#ifdef CONFIG_ADDR_MAP
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/* Initialize address mapping array */
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void init_addr_map(void)
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{
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int i;
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ppc_bat_t bat = DBAT0;
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phys_size_t size;
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unsigned long upper, lower;
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for (i = 0; i < CONFIG_SYS_NUM_ADDR_MAP; i++, bat++) {
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if (read_bat(bat, &upper, &lower) != -1) {
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if (!BATU_VALID(upper))
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size = 0;
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else
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size = BATU_SIZE(upper);
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addrmap_set_entry(BATU_VADDR(upper), BATL_PADDR(lower),
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size, i);
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}
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#ifdef CONFIG_HIGH_BATS
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/* High bats are not contiguous with low BAT numbers */
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if (bat == DBAT3)
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bat = DBAT4 - 1;
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#endif
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}
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}
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#endif
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