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689088f9da
The NovaThor U8500 SoC was released by ST-Ericsson in 2011.
It was used for some development boards like the CALAO Systems
Snowball SBC, but mass production was primarily for Android
smartphones like the Samsung Galaxy S III mini.
Previous support for U8500 was removed in
commit 68282f55b8 ("arm: Remove unused ST-Ericsson u8500 arch")
since none of the boards were converted to generic boards
before the deadline.
The new code does not have much in common with the previous code.
I have completely rewritten everything, embracing the Driver Model
and device trees wherever possible.
The U8500 support is a bit more minimal for now - my primary
use case is to use U-Boot as alternative bootloader for some of the
U8500 Samsung smartphones. At the moment U-Boot is chain-loaded from
the original Samsung bootloader. A side effect of this is that we
can (temporarily) get away without implementing some functionality
- e.g. all clocks are already enabled by the original bootloader.
More functionality will be added in future patches.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: John Rigby <john.rigby@linaro.org>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
37 lines
1,013 B
C
37 lines
1,013 B
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2019 Stephan Gerhold <stephan@gerhold.net>
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <asm/armv7.h>
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#include <asm/pl310.h>
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#define PL310_WAY_MASK 0xff
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#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
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void enable_caches(void)
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{
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/* Enable D-cache. I-cache is already enabled in start.S */
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dcache_enable();
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}
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#endif
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#ifdef CONFIG_SYS_L2_PL310
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void v7_outer_cache_disable(void)
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{
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struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
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/*
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* Linux expects the L2 cache to be turned off by the bootloader.
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* Otherwise, it fails very early (shortly after decompressing the kernel).
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*
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* On U8500, the L2 cache can be only turned on/off from the secure world.
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* Instead, prevent usage of the L2 cache by locking all ways.
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* The kernel needs to unlock them to make the L2 cache work again.
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*/
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writel(PL310_WAY_MASK, &pl310->pl310_lockdown_dbase);
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writel(PL310_WAY_MASK, &pl310->pl310_lockdown_ibase);
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}
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#endif
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