mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 08:57:58 +00:00
15647dc7fd
- fix cmd_ide.c for non ppc boards (read/write functions did not
add ATA base address)
- fix for shannon board
- #ifdef CONFIG_IDE_8xx_DIRECT some otherwise unused code
* Patch by Sangmoon Kim, 07 Oct 2003:
add support for debris board
158 lines
3.7 KiB
C
158 lines
3.7 KiB
C
/*
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* (C) Copyright 2000
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* Sangmoon Kim, Etin Systems. dogoil@etinsys.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc824x.h>
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#include <pci.h>
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int checkboard (void)
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{
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/*TODO: Check processor type */
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puts ( "Board: Debris "
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#ifdef CONFIG_MPC8240
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"8240"
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#endif
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#ifdef CONFIG_MPC8245
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"8245"
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#endif
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" ##Test not implemented yet##\n");
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return 0;
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}
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#if 0 /* NOT USED */
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int checkflash (void)
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{
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/* TODO: XXX XXX XXX */
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printf ("## Test not implemented yet ##\n");
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return (0);
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}
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#endif
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long int initdram (int board_type)
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{
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int i, cnt;
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volatile uchar * base= CFG_SDRAM_BASE;
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volatile ulong * addr;
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ulong save[32];
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ulong val, ret = 0;
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for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
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addr = (volatile ulong *)base + cnt;
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save[i++] = *addr;
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*addr = ~cnt;
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}
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addr = (volatile ulong *)base;
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save[i] = *addr;
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*addr = 0;
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if (*addr != 0) {
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*addr = save[i];
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goto Done;
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}
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for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
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addr = (volatile ulong *)base + cnt;
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val = *addr;
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*addr = save[--i];
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if (val != ~cnt) {
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/* ulong new_bank0_end = cnt * sizeof(long) - 1;
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ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
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ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
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mear1 = (mear1 & 0xFFFFFF00) |
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((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
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emear1 = (emear1 & 0xFFFFFF00) |
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((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
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mpc824x_mpc107_setreg(MEAR1, mear1);
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mpc824x_mpc107_setreg(EMEAR1, emear1);*/
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ret = cnt * sizeof(long);
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goto Done;
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}
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}
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ret = CFG_MAX_RAM_SIZE;
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Done:
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return ret;
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}
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/*
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* Initialize PCI Devices, report devices found.
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*/
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#ifndef CONFIG_PCI_PNP
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static struct pci_config_table pci_debris_config_table[] = {
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
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pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
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PCI_ENET0_MEMADDR,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
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pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
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PCI_ENET1_MEMADDR,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
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{ }
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};
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#endif
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struct pci_controller hose = {
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#ifndef CONFIG_PCI_PNP
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config_table: pci_debris_config_table,
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#endif
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};
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void pci_init_board(void)
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{
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pci_mpc824x_init(&hose);
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}
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void *nvram_read(void *dest, const long src, size_t count)
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{
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volatile uchar *d = (volatile uchar*) dest;
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volatile uchar *s = (volatile uchar*) src;
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while(count--) {
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*d++ = *s++;
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asm volatile("sync");
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}
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return dest;
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}
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void nvram_write(long dest, const void *src, size_t count)
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{
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volatile uchar *d = (volatile uchar*)dest;
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volatile uchar *s = (volatile uchar*)src;
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while(count--) {
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*d++ = *s++;
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asm volatile("sync");
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}
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}
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int misc_init_r(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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/* Write ethernet addr in NVRAM for VxWorks */
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nvram_write(CFG_ENV_ADDR + CFG_NVRAM_VXWORKS_OFFS,
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(char*)&gd->bd->bi_enetaddr[0], 6);
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return 0;
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}
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