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https://github.com/AsahiLinux/u-boot
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111fd19e3b
The multirate ethernet media access controller (mEMAC) interfaces to 10Gbps and below Ethernet/IEEE 802.3 networks via either RGMII/RMII interfaces or XAUI/XFI/SGMII/QSGMII using the high-speed SerDes interface. Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
65 lines
2.2 KiB
C
65 lines
2.2 KiB
C
/*
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* Copyright 2009-2012 Freescale Semiconductor, Inc.
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* Jun-jie Zhang <b18070@freescale.com>
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* Mingkai Hu <Mingkai.hu@freescale.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __FSL_PHY_H__
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#define __FSL_PHY_H__
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#include <net.h>
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#include <miiphy.h>
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#include <asm/fsl_enet.h>
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/* PHY register offsets */
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#define PHY_EXT_PAGE_ACCESS 0x1f
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/* MII Management Configuration Register */
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#define MIIMCFG_RESET_MGMT 0x80000000
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#define MIIMCFG_MGMT_CLOCK_SELECT 0x00000007
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#define MIIMCFG_INIT_VALUE 0x00000003
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/* MII Management Command Register */
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#define MIIMCOM_READ_CYCLE 0x00000001
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#define MIIMCOM_SCAN_CYCLE 0x00000002
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/* MII Management Address Register */
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#define MIIMADD_PHY_ADDR_SHIFT 8
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/* MII Management Indicator Register */
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#define MIIMIND_BUSY 0x00000001
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#define MIIMIND_NOTVALID 0x00000004
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void tsec_local_mdio_write(struct tsec_mii_mng *phyregs, int port_addr,
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int dev_addr, int reg, int value);
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int tsec_local_mdio_read(struct tsec_mii_mng *phyregs, int port_addr,
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int dev_addr, int regnum);
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int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum);
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int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum,
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u16 value);
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int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
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int regnum, u16 value);
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int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
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int regnum);
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struct fsl_pq_mdio_info {
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struct tsec_mii_mng *regs;
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char *name;
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};
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int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info);
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#endif /* __FSL_PHY_H__ */
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