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51f924e5ce
We need a TLB entry to call get_ram_size(); the common code doesn't create one until *after* fixed_sdram() has determined the size. So we set up tlbs for the max possible size and tear them down once we're done with get_ram_size(); the common 85xx code will then set up a final set of tlb entries for the *actual* detected size of ddr. This prevents us from having TLB entries that are larger than DDR sitting around for very long, which is not a recommended scenario. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
436 lines
12 KiB
C
436 lines
12 KiB
C
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/*
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* (C) Copyright 2005
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/immap_85xx.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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struct sdram_conf_s {
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unsigned long size;
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unsigned long reg;
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#ifdef CONFIG_TQM8548
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unsigned long refresh;
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#endif /* CONFIG_TQM8548 */
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};
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typedef struct sdram_conf_s sdram_conf_t;
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#ifdef CONFIG_TQM8548
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#ifdef CONFIG_TQM8548_AG
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sdram_conf_t ddr_cs_conf[] = {
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{(1024 << 20), 0x80044202, 0x0002D000}, /* 1024MB, 14x10(4) */
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{ (512 << 20), 0x80044102, 0x0001A000}, /* 512MB, 13x10(4) */
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{ (256 << 20), 0x80040102, 0x00014000}, /* 256MB, 13x10(4) */
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{ (128 << 20), 0x80040101, 0x0000C000}, /* 128MB, 13x9(4) */
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};
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#else /* !CONFIG_TQM8548_AG */
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sdram_conf_t ddr_cs_conf[] = {
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{(512 << 20), 0x80044102, 0x0001A000}, /* 512MB, 13x10(4) */
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{(256 << 20), 0x80040102, 0x00014000}, /* 256MB, 13x10(4) */
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{(128 << 20), 0x80040101, 0x0000C000}, /* 128MB, 13x9(4) */
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};
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#endif /* CONFIG_TQM8548_AG */
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#else /* !CONFIG_TQM8548 */
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sdram_conf_t ddr_cs_conf[] = {
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{(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */
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{(256 << 20), 0x80000102}, /* 256MB, 13x10(4) */
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{(128 << 20), 0x80000101}, /* 128MB, 13x9(4) */
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{( 64 << 20), 0x80000001}, /* 64MB, 12x9(4) */
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};
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#endif /* CONFIG_TQM8548 */
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#define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0]))
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int cas_latency (void);
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static phys_size_t sdram_setup(int);
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/*
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* Autodetect onboard DDR SDRAM on 85xx platforms
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*
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* NOTE: Some of the hardcoded values are hardware dependant,
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* so this should be extended for other future boards
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* using this routine!
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*/
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phys_size_t fixed_sdram(void)
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{
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int casl = 0;
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phys_size_t dram_size = 0;
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casl = cas_latency();
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dram_size = sdram_setup(casl);
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if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) {
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/*
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* Try again with default CAS latency
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*/
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printf("Problem with CAS lantency, using default CL %d/10!\n",
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CONFIG_DDR_DEFAULT_CL);
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dram_size = sdram_setup(CONFIG_DDR_DEFAULT_CL);
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puts(" ");
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}
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return dram_size;
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}
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static phys_size_t sdram_setup(int casl)
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{
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int i;
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volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
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#ifdef CONFIG_TQM8548
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
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volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
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#endif
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#else /* !CONFIG_TQM8548 */
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unsigned long cfg_ddr_timing1;
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unsigned long cfg_ddr_mode;
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#endif /* CONFIG_TQM8548 */
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/*
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* Disable memory controller.
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*/
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ddr->cs0_config = 0;
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ddr->sdram_cfg = 0;
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#ifdef CONFIG_TQM8548
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/* Timing and refresh settings for DDR2-533 and below */
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ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
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ddr->cs0_config = ddr_cs_conf[0].reg;
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ddr->timing_cfg_3 = 0x00020000;
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/* TIMING CFG 1, 533MHz
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* PRETOACT: 4 Clocks
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* ACTTOPRE: 12 Clocks
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* ACTTORW: 4 Clocks
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* CASLAT: 4 Clocks
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* REFREC: EXT_REFREC:REFREC 53 Clocks
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* WRREC: 4 Clocks
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* ACTTOACT: 3 Clocks
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* WRTORD: 2 Clocks
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*/
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ddr->timing_cfg_1 = 0x4C47D432;
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/* TIMING CFG 2, 533MHz
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* ADD_LAT: 3 Clocks
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* CPO: READLAT + 1
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* WR_LAT: 3 Clocks
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* RD_TO_PRE: 2 Clocks
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* WR_DATA_DELAY: 1/2 Clock
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* CKE_PLS: 3 Clock
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* FOUR_ACT: 14 Clocks
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*/
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ddr->timing_cfg_2 = 0x331848CE;
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/* DDR SDRAM Mode, 533MHz
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* MRS: Extended Mode Register
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* OUT: Outputs enabled
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* RDQS: no
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* DQS: enabled
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* OCD: default state
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* RTT: 75 Ohms
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* Posted CAS: 3 Clocks
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* ODS: reduced strength
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* DLL: enabled
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* MR: Mode Register
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* PD: fast exit
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* WR: 4 Clocks
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* DLL: no DLL reset
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* TM: normal
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* CAS latency: 4 Clocks
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* BT: sequential
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* Burst length: 4
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*/
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ddr->sdram_mode = 0x439E0642;
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/* DDR SDRAM Interval, 533MHz
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* REFINT: 1040 Clocks
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* BSTOPRE: 256
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*/
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ddr->sdram_interval = (1040 << 16) | 0x100;
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/*
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* Workaround for erratum DDR19 according to MPC8548 Device Errata
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* document, Rev. 1: DDR IO receiver must be set to an acceptable
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* bias point by modifying a hidden register.
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*/
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if (SVR_REV (get_svr ()) < 0x21)
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gur->ddrioovcr = 0x90000000; /* enable, VSEL 1.8V */
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/* DDR SDRAM CFG 2
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* FRC_SR: normal mode
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* SR_IE: no self-refresh interrupt
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* DLL_RST_DIS: don't care, leave at reset value
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* DQS_CFG: differential DQS signals
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* ODT_CFG: assert ODT to internal IOs only during reads to DRAM
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* LVWx_CFG: don't care, leave at reset value
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* NUM_PR: 1 refresh will be issued at a time
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* DM_CFG: don't care, leave at reset value
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* D_INIT: no data initialization
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*/
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ddr->sdram_cfg_2 = 0x04401000;
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/* DDR SDRAM MODE 2
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* MRS: Extended Mode Register 2
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*/
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ddr->sdram_mode_2 = 0x8000C000;
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/* DDR SDRAM CLK CNTL
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* CLK_ADJUST: 1/2 Clock 0x02000000
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* CLK_ADJUST: 5/8 Clock 0x02800000
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*/
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ddr->sdram_clk_cntl = 0x02800000;
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/* wait for clock stabilization */
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asm ("sync;isync;msync");
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udelay (1000);
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#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
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/*
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* Workaround for erratum DDR20 according to MPC8548 Device Errata
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* document, Rev. 1: "CKE signal may not function correctly after
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* assertion of HRESET"
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*/
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/* 1. Configure DDR register as is done in normal DDR configuration.
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* Do not set DDR_SDRAM_CFG[MEM_EN].
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*
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* 2. Set reserved bit EEBACR[3] at offset 0x1000
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*/
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ecm->eebacr |= 0x10000000;
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/*
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* 3. Before DDR_SDRAM_CFG[MEM_EN] is set, write DDR_SDRAM_CFG_2[D_INIT]
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*
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* DDR_SDRAM_CFG_2:
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* FRC_SR: normal mode
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* SR_IE: no self-refresh interrupt
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* DLL_RST_DIS: don't care, leave at reset value
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* DQS_CFG: differential DQS signals
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* ODT_CFG: assert ODT to internal IOs only during reads to DRAM
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* LVWx_CFG: don't care, leave at reset value
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* NUM_PR: 1 refresh will be issued at a time
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* DM_CFG: don't care, leave at reset value
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* D_INIT: enable data initialization
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*/
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ddr->sdram_cfg_2 |= 0x00000010;
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/*
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* 4. Before DDR_SDRAM_CFG[MEM_EN] set, write D3[21] to disable data
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* training
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*/
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ddr->debug[2] |= 0x00000400;
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/*
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* 5. Wait 200 micro-seconds
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*/
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udelay (200);
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/*
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* 6. Set DDR_SDRAM_CFG[MEM_EN]
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*
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* BTW, initialize DDR_SDRAM_CFG:
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* MEM_EN: enabled
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* SREN: don't care, leave at reset value
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* ECC_EN: no error report
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* RD_EN: no registered DIMMs
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* SDRAM_TYPE: DDR2
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* DYN_PWR: no power management
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* 32_BE: don't care, leave at reset value
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* 8_BE: 4 beat burst
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* NCAP: don't care, leave at reset value
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* 2T_EN: 1T Timing
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* BA_INTLV_CTL: no interleaving
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* x32_EN: x16 organization
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* PCHB8: MA[10] for auto-precharge
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* HSE: half strength for single and 2-layer stacks
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* (full strength for 3- and 4-layer stacks not
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* yet considered)
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* MEM_HALT: no halt
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* BI: automatic initialization
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*/
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ddr->sdram_cfg = 0x83000008;
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/*
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* 7. Poll DDR_SDRAM_CFG_2[D_INIT] until it is cleared by hardware
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*/
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asm ("sync;isync;msync");
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while (ddr->sdram_cfg_2 & 0x00000010)
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asm ("eieio");
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/*
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* 8. Clear D3[21] to re-enable data training
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*/
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ddr->debug[2] &= ~0x00000400;
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/*
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* 9. Set D2(21) to force data training to run
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*/
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ddr->debug[1] |= 0x00000400;
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/*
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* 10. Poll on D2[21] until it is cleared by hardware
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*/
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asm ("sync;isync;msync");
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while (ddr->debug[1] & 0x00000400)
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asm ("eieio");
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/*
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* 11. Clear reserved bit EEBACR[3] at offset 0x1000
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*/
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ecm->eebacr &= ~0x10000000;
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#else /* !(CONFIG_TQM8548_AG || CONFIG_TQM8548_BE) */
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/* DDR SDRAM CLK CNTL
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* MEM_EN: enabled
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* SREN: don't care, leave at reset value
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* ECC_EN: no error report
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* RD_EN: no register DIMMs
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* SDRAM_TYPE: DDR2
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* DYN_PWR: no power management
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* 32_BE: don't care, leave at reset value
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* 8_BE: 4 beat burst
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* NCAP: don't care, leave at reset value
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* 2T_EN: 1T Timing
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* BA_INTLV_CTL: no interleaving
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* x32_EN: x16 organization
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* PCHB8: MA[10] for auto-precharge
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* HSE: half strength for single and 2-layer stacks
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* (full strength for 3- and 4-layer stacks no yet considered)
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* MEM_HALT: no halt
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* BI: automatic initialization
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*/
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ddr->sdram_cfg = 0x83000008;
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#endif /* CONFIG_TQM8548_AG || CONFIG_TQM8548_BE */
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asm ("sync; isync; msync");
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udelay (1000);
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#else /* !CONFIG_TQM8548 */
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switch (casl) {
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case 20:
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cfg_ddr_timing1 = 0x47405331 | (3 << 16);
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cfg_ddr_mode = 0x40020002 | (2 << 4);
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break;
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case 25:
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cfg_ddr_timing1 = 0x47405331 | (4 << 16);
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cfg_ddr_mode = 0x40020002 | (6 << 4);
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break;
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case 30:
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default:
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cfg_ddr_timing1 = 0x47405331 | (5 << 16);
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cfg_ddr_mode = 0x40020002 | (3 << 4);
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break;
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}
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ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
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ddr->cs0_config = ddr_cs_conf[0].reg;
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ddr->timing_cfg_1 = cfg_ddr_timing1;
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ddr->timing_cfg_2 = 0x00000800; /* P9-45,may need tuning */
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ddr->sdram_mode = cfg_ddr_mode;
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ddr->sdram_interval = 0x05160100; /* autocharge,no open page */
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ddr->err_disable = 0x0000000D;
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asm ("sync; isync; msync");
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udelay (1000);
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ddr->sdram_cfg = 0xc2000000; /* unbuffered,no DYN_PWR */
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asm ("sync; isync; msync");
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udelay (1000);
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#endif /* CONFIG_TQM8548 */
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/*
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* get_ram_size() depends on having tlbs for the DDR, but they are
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* not yet setup because we don't know the size. Set up a temp
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* mapping and delete it when done.
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*/
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setup_ddr_tlbs(CONFIG_SYS_DDR_EARLY_SIZE_MB);
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for (i = 0; i < N_DDR_CS_CONF; i++) {
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ddr->cs0_config = ddr_cs_conf[i].reg;
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if (get_ram_size (0, ddr_cs_conf[i].size) ==
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ddr_cs_conf[i].size) {
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/*
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* size detected -> set Chip Select Bounds Register
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*/
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ddr->cs0_bnds = (ddr_cs_conf[i].size - 1) >> 24;
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break;
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}
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}
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clear_ddr_tlbs(CONFIG_SYS_DDR_EARLY_SIZE_MB);
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#ifdef CONFIG_TQM8548
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if (i < N_DDR_CS_CONF) {
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/* Adjust refresh rate for DDR2 */
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ddr->timing_cfg_3 = ddr_cs_conf[i].refresh & 0x00070000;
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ddr->timing_cfg_1 = (ddr->timing_cfg_1 & 0xFFFF0FFF) |
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(ddr_cs_conf[i].refresh & 0x0000F000);
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return ddr_cs_conf[i].size;
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}
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#endif /* CONFIG_TQM8548 */
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/* return size if detected, else return 0 */
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return (i < N_DDR_CS_CONF) ? ddr_cs_conf[i].size : 0;
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}
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#if defined(CONFIG_SYS_DRAM_TEST)
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int testdram (void)
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{
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uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
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uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
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uint *p;
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printf ("SDRAM test phase 1:\n");
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for (p = pstart; p < pend; p++)
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*p = 0xaaaaaaaa;
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for (p = pstart; p < pend; p++) {
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if (*p != 0xaaaaaaaa) {
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printf ("SDRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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printf ("SDRAM test phase 2:\n");
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for (p = pstart; p < pend; p++)
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*p = 0x55555555;
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for (p = pstart; p < pend; p++) {
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if (*p != 0x55555555) {
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printf ("SDRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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printf ("SDRAM test passed.\n");
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return 0;
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}
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#endif
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