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B4420 is a reduced personality of B4860 with fewer core/clusters(both SC3900 and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and reduced target frequencies. Key differences between B4860 and B4420 ---------------------------------------- B4420 has: 1. Fewer e6500 cores: 1 cluster with 2 e6500 cores 2. Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster. 3. Single DDRC 4. 2X 4 lane serdes 5. 3 SGMII interfaces 6. no sRIO 7. no 10G Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
222 lines
6.2 KiB
C
222 lines
6.2 KiB
C
/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/fsl_serdes.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include "fsl_corenet2_serdes.h"
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struct serdes_config {
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u8 protocol;
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u8 lanes[SRDS_MAX_LANES];
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};
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#ifdef CONFIG_PPC_B4860
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static struct serdes_config serdes1_cfg_tbl[] = {
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/* SerDes 1 */
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{0x0D, {CPRI8, CPRI7, CPRI6, CPRI5,
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CPRI4, CPRI3, CPRI2, CPRI1}},
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{0x0E, {CPRI8, CPRI7, CPRI6, CPRI5,
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CPRI4, CPRI3, CPRI2, CPRI1}},
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{0x12, {CPRI8, CPRI7, CPRI6, CPRI5,
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CPRI4, CPRI3, CPRI2, CPRI1}},
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{0x2a, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
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CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
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{0x2C, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
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CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
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{0x2D, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
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CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
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{0x2E, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
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CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
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{0x30, {AURORA, AURORA,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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CPRI4, CPRI3, CPRI2, CPRI1}},
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{0x32, {AURORA, AURORA,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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CPRI4, CPRI3, CPRI2, CPRI1}},
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{0x33, {AURORA, AURORA,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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CPRI4, CPRI3, CPRI2, CPRI1}},
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{0x34, {AURORA, AURORA,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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CPRI4, CPRI3, CPRI2, CPRI1}},
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{0x3E, {CPRI8, CPRI7, CPRI6, CPRI5,
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CPRI4, CPRI3, CPRI2, CPRI1}},
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{}
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};
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static struct serdes_config serdes2_cfg_tbl[] = {
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/* SerDes 2 */
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{0x18, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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AURORA, AURORA, SRIO1, SRIO1}},
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{0x1D, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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AURORA, AURORA, SRIO1, SRIO1}},
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{0x2B, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SRIO2, SRIO2,
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AURORA, AURORA, SRIO1, SRIO1}},
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{0x30, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SRIO2, SRIO2,
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AURORA, AURORA,
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SRIO1, SRIO1}},
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{0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, AURORA,
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SRIO1, SRIO1, SRIO1, SRIO1}},
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{0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, AURORA,
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SRIO1, SRIO1, SRIO1, SRIO1}},
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{0x4C, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, AURORA,
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SRIO1, SRIO1, SRIO1, SRIO1}},
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{0x4E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, AURORA,
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SRIO1, SRIO1, SRIO1, SRIO1}},
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{0x7A, {SRIO2, SRIO2, SRIO2, SRIO2,
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SRIO1, SRIO1, SRIO1, SRIO1}},
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{0x84, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SRIO2, SRIO2, AURORA, AURORA,
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XFI_FM1_MAC9, XFI_FM1_MAC10}},
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{0x85, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SRIO2, SRIO2, AURORA, AURORA,
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XFI_FM1_MAC9, XFI_FM1_MAC10}},
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{0x87, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SRIO2, SRIO2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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XFI_FM1_MAC9, XFI_FM1_MAC10}},
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{0x8D, {SRIO2, SRIO2, SRIO2, SRIO2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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XFI_FM1_MAC9, XFI_FM1_MAC10}},
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{0x93, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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XAUI_FM1_MAC10, XAUI_FM1_MAC10,
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XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
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{0x9E, {PCIE1, PCIE1, PCIE1, PCIE1,
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XAUI_FM1_MAC10, XAUI_FM1_MAC10,
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XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
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{0x9A, {PCIE1, PCIE1,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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XAUI_FM1_MAC10, XAUI_FM1_MAC10,
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XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
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{0xB2, {PCIE1, PCIE1, PCIE1, PCIE1,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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XFI_FM1_MAC9, XFI_FM1_MAC10}},
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{0xC3, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
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XAUI_FM1_MAC9, XAUI_FM1_MAC9,
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SRIO1, SRIO1, SRIO1, SRIO1}},
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{0x98, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
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XAUI_FM1_MAC9, XAUI_FM1_MAC9,
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XAUI_FM1_MAC10, XAUI_FM1_MAC10,
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XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
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{}
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};
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#endif
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#ifdef CONFIG_PPC_B4420
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static struct serdes_config serdes1_cfg_tbl[] = {
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{0x0D, {NONE, NONE, CPRI6, CPRI5,
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CPRI4, CPRI3, NONE, NONE} },
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{0x0E, {NONE, NONE, CPRI8, CPRI5,
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CPRI4, CPRI3, NONE, NONE} },
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{0x0F, {NONE, NONE, CPRI6, CPRI5,
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CPRI4, CPRI3, NONE, NONE} },
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{0x18, {NONE, NONE,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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NONE, NONE, NONE, NONE} },
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{0x1B, {NONE, NONE,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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NONE, NONE, NONE, NONE} },
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{0x1E, {NONE, NONE, AURORA, AURORA,
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NONE, NONE, NONE, NONE} },
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{0x21, {NONE, NONE, AURORA, AURORA,
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NONE, NONE, NONE, NONE} },
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{0x3E, {NONE, NONE, CPRI6, CPRI5,
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CPRI4, CPRI3, NONE, NONE} },
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{}
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};
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static struct serdes_config serdes2_cfg_tbl[] = {
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{0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, AURORA,
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NONE, NONE, NONE, NONE} },
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{0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, AURORA,
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NONE, NONE, NONE, NONE} },
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{0x6F, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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AURORA, AURORA, NONE, NONE, NONE, NONE} },
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{0x70, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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AURORA, AURORA, NONE, NONE, NONE, NONE} },
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{0x9A, {PCIE1, PCIE1,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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NONE, NONE, NONE, NONE} },
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{0x9E, {PCIE1, PCIE1, PCIE1, PCIE1,
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NONE, NONE, NONE, NONE} },
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{}
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};
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#endif
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static struct serdes_config *serdes_cfg_tbl[] = {
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serdes1_cfg_tbl,
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serdes2_cfg_tbl,
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};
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enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
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{
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struct serdes_config *ptr;
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if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
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return 0;
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ptr = serdes_cfg_tbl[serdes];
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while (ptr->protocol) {
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if (ptr->protocol == cfg)
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return ptr->lanes[lane];
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ptr++;
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}
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return 0;
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}
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int is_serdes_prtcl_valid(int serdes, u32 prtcl)
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{
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int i;
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struct serdes_config *ptr;
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if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
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return 0;
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ptr = serdes_cfg_tbl[serdes];
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while (ptr->protocol) {
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if (ptr->protocol == prtcl)
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break;
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ptr++;
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}
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if (!ptr->protocol)
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return 0;
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for (i = 0; i < SRDS_MAX_LANES; i++) {
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if (ptr->lanes[i] != NONE)
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return 1;
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}
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return 0;
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}
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