mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-14 23:33:00 +00:00
ae3527f088
We add RISC-V semihosting based serial console for JTAG based early debugging. The RISC-V semihosting specification is available at: https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
46 lines
1.4 KiB
Makefile
46 lines
1.4 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# Copyright (C) 2017 Andes Technology Corporation
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# Rick Chen, Andes Technology Corporation <rick@andestech.com>
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obj-$(CONFIG_CMD_BOOTM) += bootm.o
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obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
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obj-$(CONFIG_CMD_GO) += boot.o
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obj-y += cache.o
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obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o
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ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
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obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o
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obj-$(CONFIG_ANDES_PLICSW) += andes_plicsw.o
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else
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obj-$(CONFIG_SBI) += sbi.o
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obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
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endif
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obj-y += interrupts.o
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ifeq ($(CONFIG_$(SPL_)SYSRESET),)
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obj-y += reset.o
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endif
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obj-y += setjmp.o
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obj-$(CONFIG_$(SPL_)SMP) += smp.o
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obj-$(CONFIG_SPL_BUILD) += spl.o
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obj-y += fdt_fixup.o
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# For building EFI apps
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CFLAGS_NON_EFI := -fstack-protector-strong
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CFLAGS_$(EFI_CRT0) := $(CFLAGS_EFI)
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CFLAGS_REMOVE_$(EFI_CRT0) := $(CFLAGS_NON_EFI)
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CFLAGS_$(EFI_RELOC) := $(CFLAGS_EFI)
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CFLAGS_REMOVE_$(EFI_RELOC) := $(CFLAGS_NON_EFI)
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extra-$(CONFIG_CMD_BOOTEFI_HELLO_COMPILE) += $(EFI_CRT0) $(EFI_RELOC)
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extra-$(CONFIG_CMD_BOOTEFI_SELFTEST) += $(EFI_CRT0) $(EFI_RELOC)
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extra-$(CONFIG_EFI) += $(EFI_CRT0) $(EFI_RELOC)
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obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o
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obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMMOVE) += memmove.o
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obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o
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obj-$(CONFIG_$(SPL_TPL_)SEMIHOSTING) += semihosting.o
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