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This training code provides run-time adjustment of DDR PHY parameters for stable DDR operation. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> |
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bcu_init.c | ||
board_info.c | ||
boot-mode.c | ||
clkrst_init.c | ||
ddrphy_init.c | ||
Makefile | ||
pinctrl.c | ||
platdevice.c | ||
pll_init.c | ||
pll_spectrum.c | ||
sbc_init.c | ||
sg_init.c | ||
umc_init.c |