mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-11 13:56:30 +00:00
ffee1dde3c
Fix PHY addresses for QSGMII Riser Card working in SGMII mode on board P3041/P5020/P4080/P5040/B4860. QSGMII Riser Card can work in SGMII mode, but having the different PHY addresses. So the following steps should be done: 1. Confirm whether QSGMII Riser Card is used. 2. If yes, set the proper PHY address. Generally, the function is_qsgmii_riser_card() is for step 1, and set_sgmii_phy() for step 2. However, there are still some special situations, take P5040 and B4860 as examples, the PHY addresses need to be changed when serdes protocol is changed, so it is necessary to confirm the protocol before setting PHY addresses. Signed-off-by: Zhao Qiang <B45475@freescale.com>
29 lines
599 B
C
29 lines
599 B
C
/*
|
|
* Copyright 2012 Freescale Semiconductor, Inc.
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#ifndef __B4860QDS_QIXIS_H__
|
|
#define __B4860QDS_QIXIS_H__
|
|
|
|
/* Definitions of QIXIS Registers for B4860QDS */
|
|
|
|
/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
|
|
#define BRDCFG4_EMISEL_MASK 0xE0
|
|
#define BRDCFG4_EMISEL_SHIFT 5
|
|
|
|
/* CLK */
|
|
#define QIXIS_CLK_66 0x0
|
|
#define QIXIS_CLK_100 0x1
|
|
#define QIXIS_CLK_125 0x2
|
|
#define QIXIS_CLK_133 0x3
|
|
|
|
#define QIXIS_SRDS1CLK_122 0x5a
|
|
#define QIXIS_SRDS1CLK_125 0x5e
|
|
|
|
/* SGMII */
|
|
#define PHY_BASE_ADDR 0x18
|
|
#define PORT_NUM 0x04
|
|
#define REGNUM 0x00
|
|
#endif
|