mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-25 22:20:45 +00:00
401d1c4f5d
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
90 lines
2 KiB
C
90 lines
2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* Copyright 2020 NXP
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <env.h>
|
|
#include <init.h>
|
|
#include <malloc.h>
|
|
#include <errno.h>
|
|
#include <asm/global_data.h>
|
|
#include <asm/io.h>
|
|
#include <miiphy.h>
|
|
#include <netdev.h>
|
|
#include <asm/mach-imx/iomux-v3.h>
|
|
#include <asm-generic/gpio.h>
|
|
#include <fsl_esdhc_imx.h>
|
|
#include <mmc.h>
|
|
#include <asm/arch/imx8mq_pins.h>
|
|
#include <asm/arch/sys_proto.h>
|
|
#include <asm/mach-imx/gpio.h>
|
|
#include <asm/arch/clock.h>
|
|
#include <spl.h>
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
|
|
|
|
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
|
|
|
|
static iomux_v3_cfg_t const wdog_pads[] = {
|
|
IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
|
|
};
|
|
|
|
static iomux_v3_cfg_t const uart_pads[] = {
|
|
IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
|
IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
|
};
|
|
|
|
int board_early_init_f(void)
|
|
{
|
|
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
|
|
|
|
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
|
|
set_wdog_reset(wdog);
|
|
|
|
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_FEC_MXC
|
|
static int setup_fec(void)
|
|
{
|
|
struct iomuxc_gpr_base_regs *gpr =
|
|
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
|
|
|
|
/* Use 125M anatop REF_CLK1 for ENET1, not from external */
|
|
clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
|
|
return set_clk_enet(ENET_125MHZ);
|
|
}
|
|
|
|
int board_phy_config(struct phy_device *phydev)
|
|
{
|
|
/* enable rgmii rxc skew and phy mode select to RGMII copper */
|
|
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
|
|
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
|
|
|
|
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
|
|
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
|
|
|
|
if (phydev->drv->config)
|
|
phydev->drv->config(phydev);
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
int board_init(void)
|
|
{
|
|
#ifdef CONFIG_FEC_MXC
|
|
setup_fec();
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
int board_mmc_get_env_dev(int devno)
|
|
{
|
|
return devno;
|
|
}
|