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325 lines
11 KiB
C
325 lines
11 KiB
C
/**
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* @file IxEthAcc_p.h
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*
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* @author Intel Corporation
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* @date 12-Feb-2002
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*
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* @brief Internal Header file for IXP425 Ethernet Access component.
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*
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* Design Notes:
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*
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*
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* @par
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* IXP400 SW Release version 2.0
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*
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* -- Copyright Notice --
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*
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* @par
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* Copyright 2001-2005, Intel Corporation.
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* All rights reserved.
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*
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* @par
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @par
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* -- End of Copyright Notice --
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*/
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/**
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* @addtogroup IxEthAccPri
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*@{
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*/
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#ifndef IxEthAcc_p_H
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#define IxEthAcc_p_H
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/*
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* Os/System dependancies.
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*/
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#include "IxOsal.h"
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/*
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* Intermodule dependancies
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*/
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#include "IxNpeDl.h"
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#include "IxQMgr.h"
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#include "IxEthNpe.h"
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/*
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* Intra module dependancies
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*/
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#include "IxEthAccDataPlane_p.h"
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#include "IxEthAccMac_p.h"
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#define INLINE __inline__
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#ifdef NDEBUG
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#define IX_ETH_ACC_PRIVATE static
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#else
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#define IX_ETH_ACC_PRIVATE
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#endif /* ndef NDEBUG */
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#define IX_ETH_ACC_PUBLIC
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#define IX_ETH_ACC_IS_PORT_VALID(port) ((port) < IX_ETH_ACC_NUMBER_OF_PORTS ? TRUE : FALSE )
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#ifndef NDEBUG
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#define IX_ETH_ACC_FATAL_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_FATAL,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
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#define IX_ETH_ACC_WARNING_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_WARNING,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
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#define IX_ETH_ACC_DEBUG_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_FATAL,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
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#else
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#define IX_ETH_ACC_FATAL_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_FATAL,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
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#define IX_ETH_ACC_WARNING_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_WARNING,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
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#define IX_ETH_ACC_DEBUG_LOG(a,b,c,d,e,f,g) {}
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#endif
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IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccInitDataPlane(void);
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IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccQMgrQueuesConfig(void);
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IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccQMgrRxCallbacksRegister(IxQMgrCallback ixQMgrCallback);
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IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccSingleEthNpeCheck(IxEthAccPortId portId);
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IX_ETH_ACC_PUBLIC void ixEthAccQMgrRxQEntryGet(UINT32 *numRxQueueEntries);
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/* prototypes for the private control plane functions (used by the control interface wrapper) */
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IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortEnablePriv(IxEthAccPortId portId);
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IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortDisablePriv(IxEthAccPortId portId);
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IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortEnabledQueryPriv(IxEthAccPortId portId, BOOL *enabled);
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IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortPromiscuousModeClearPriv(IxEthAccPortId portId);
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IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortPromiscuousModeSetPriv(IxEthAccPortId portId);
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IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortUnicastMacAddressSetPriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr);
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IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortUnicastMacAddressGetPriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr);
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IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressJoinPriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr);
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IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressJoinAllPriv(IxEthAccPortId portId);
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IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressLeavePriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr);
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IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressLeaveAllPriv(IxEthAccPortId portId);
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IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortUnicastAddressShowPriv(IxEthAccPortId portId);
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IX_ETH_ACC_PUBLIC void ixEthAccPortMulticastAddressShowPriv(IxEthAccPortId portId);
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IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortDuplexModeSetPriv(IxEthAccPortId portId, IxEthAccDuplexMode mode);
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IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortDuplexModeGetPriv(IxEthAccPortId portId, IxEthAccDuplexMode *mode);
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IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendPaddingEnablePriv(IxEthAccPortId portId);
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IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendPaddingDisablePriv(IxEthAccPortId portId);
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IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendFCSEnablePriv(IxEthAccPortId portId);
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IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendFCSDisablePriv(IxEthAccPortId portId);
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IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortRxFrameAppendFCSEnablePriv(IxEthAccPortId portId);
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IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortRxFrameAppendFCSDisablePriv(IxEthAccPortId portId);
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IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccTxSchedulingDisciplineSetPriv(IxEthAccPortId portId, IxEthAccSchedulerDiscipline sched);
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IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccRxSchedulingDisciplineSetPriv(IxEthAccSchedulerDiscipline sched);
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/**
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* @struct ixEthAccRxDataStats
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* @brief Stats data structures for data path. - Not obtained from h/w
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*
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*/
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typedef struct
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{
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UINT32 rxFrameClientCallback;
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UINT32 rxFreeRepOK;
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UINT32 rxFreeRepDelayed;
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UINT32 rxFreeRepFromSwQOK;
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UINT32 rxFreeRepFromSwQDelayed;
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UINT32 rxFreeLateNotificationEnabled;
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UINT32 rxFreeLowCallback;
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UINT32 rxFreeOverflow;
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UINT32 rxFreeLock;
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UINT32 rxDuringDisable;
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UINT32 rxSwQDuringDisable;
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UINT32 rxUnlearnedMacAddress;
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UINT32 rxPriority[IX_ETH_ACC_TX_PRIORITY_7 + 1];
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UINT32 rxUnexpectedError;
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UINT32 rxFiltered;
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} IxEthAccRxDataStats;
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/**
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* @struct IxEthAccTxDataStats
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* @brief Stats data structures for data path. - Not obtained from h/w
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*
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*/
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typedef struct
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{
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UINT32 txQOK;
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UINT32 txQDelayed;
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UINT32 txFromSwQOK;
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UINT32 txFromSwQDelayed;
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UINT32 txLowThreshCallback;
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UINT32 txDoneClientCallback;
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UINT32 txDoneClientCallbackDisable;
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UINT32 txOverflow;
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UINT32 txLock;
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UINT32 txPriority[IX_ETH_ACC_TX_PRIORITY_7 + 1];
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UINT32 txLateNotificationEnabled;
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UINT32 txDoneDuringDisable;
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UINT32 txDoneSwQDuringDisable;
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UINT32 txUnexpectedError;
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} IxEthAccTxDataStats;
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/* port Disable state machine : list of states */
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typedef enum
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{
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/* general port states */
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DISABLED = 0,
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ACTIVE,
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/* particular Tx/Rx states */
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REPLENISH,
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RECEIVE,
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TRANSMIT,
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TRANSMIT_DONE
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} IxEthAccPortDisableState;
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typedef struct
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{
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BOOL fullDuplex;
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BOOL rxFCSAppend;
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BOOL txFCSAppend;
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BOOL txPADAppend;
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BOOL enabled;
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BOOL promiscuous;
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BOOL joinAll;
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IxOsalMutex ackMIBStatsLock;
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IxOsalMutex ackMIBStatsResetLock;
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IxOsalMutex MIBStatsGetAccessLock;
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IxOsalMutex MIBStatsGetResetAccessLock;
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IxOsalMutex npeLoopbackMessageLock;
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IxEthAccMacAddr mcastAddrsTable[IX_ETH_ACC_MAX_MULTICAST_ADDRESSES];
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UINT32 mcastAddrIndex;
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IX_OSAL_MBUF *portDisableTxMbufPtr;
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IX_OSAL_MBUF *portDisableRxMbufPtr;
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volatile IxEthAccPortDisableState portDisableState;
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volatile IxEthAccPortDisableState rxState;
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volatile IxEthAccPortDisableState txState;
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BOOL initDone;
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BOOL macInitialised;
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} IxEthAccMacState;
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/**
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* @struct IxEthAccRxInfo
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* @brief System-wide data structures associated with the data plane.
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*
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*/
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typedef struct
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{
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IxQMgrQId higherPriorityQueue[IX_QMGR_MAX_NUM_QUEUES]; /**< higher priority queue list */
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IxEthAccSchedulerDiscipline schDiscipline; /**< Receive Xscale QoS type */
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} IxEthAccInfo;
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/**
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* @struct IxEthAccRxDataInfo
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* @brief Per Port data structures associated with the receive data plane.
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*
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*/
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typedef struct
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{
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IxQMgrQId rxFreeQueue; /**< rxFree Queue for this port */
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IxEthAccPortRxCallback rxCallbackFn;
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UINT32 rxCallbackTag;
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IxEthAccDataPlaneQList freeBufferList;
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IxEthAccPortMultiBufferRxCallback rxMultiBufferCallbackFn;
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UINT32 rxMultiBufferCallbackTag;
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BOOL rxMultiBufferCallbackInUse;
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IxEthAccRxDataStats stats; /**< Receive s/w stats */
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} IxEthAccRxDataInfo;
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/**
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* @struct IxEthAccTxDataInfo
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* @brief Per Port data structures associated with the transmit data plane.
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*
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*/
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typedef struct
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{
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IxEthAccPortTxDoneCallback txBufferDoneCallbackFn;
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UINT32 txCallbackTag;
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IxEthAccDataPlaneQList txQ[IX_ETH_ACC_NUM_TX_PRIORITIES]; /**< Transmit Q */
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IxEthAccSchedulerDiscipline schDiscipline; /**< Transmit Xscale QoS */
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IxQMgrQId txQueue; /**< txQueue for this port */
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IxEthAccTxDataStats stats; /**< Transmit s/w stats */
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} IxEthAccTxDataInfo;
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/**
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* @struct IxEthAccPortDataInfo
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* @brief Per Port data structures associated with the port data plane.
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*
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*/
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typedef struct
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{
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BOOL portInitialized;
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UINT32 npeId; /**< NpeId for this port */
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IxEthAccTxDataInfo ixEthAccTxData; /**< Transmit data control structures */
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IxEthAccRxDataInfo ixEthAccRxData; /**< Recieve data control structures */
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} IxEthAccPortDataInfo;
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extern IxEthAccPortDataInfo ixEthAccPortData[];
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#define IX_ETH_IS_PORT_INITIALIZED(port) (ixEthAccPortData[port].portInitialized)
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extern BOOL ixEthAccServiceInit;
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#define IX_ETH_ACC_IS_SERVICE_INITIALIZED() (ixEthAccServiceInit == TRUE )
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/*
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* Maximum number of frames to consume from the Rx Frame Q.
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*/
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#define IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK (128)
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/*
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* Max number of times to load the Rx Free Q from callback.
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*/
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#define IX_ETH_ACC_MAX_RX_FREE_BUFFERS_LOAD (256) /* Set greater than depth of h/w Q + drain time at line rate */
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/*
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* Max number of times to read from the Tx Done Q in one sitting.
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*/
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#define IX_ETH_ACC_MAX_TX_FRAME_DONE_CONSUME_PER_CALLBACK (256)
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/*
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* Max number of times to take buffers from S/w queues and write them to the H/w Tx
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* queues on receipt of a Tx low threshold callback
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*/
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#define IX_ETH_ACC_MAX_TX_FRAME_TX_CONSUME_PER_CALLBACK (16)
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#define IX_ETH_ACC_FLUSH_CACHE(addr,size) IX_OSAL_CACHE_FLUSH((addr),(size))
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#define IX_ETH_ACC_INVALIDATE_CACHE(addr,size) IX_OSAL_CACHE_INVALIDATE((addr),(size))
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#define IX_ETH_ACC_MEMSET(start,value,size) memset(start,value,size)
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#endif /* ndef IxEthAcc_p_H */
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