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248 lines
8.5 KiB
C
248 lines
8.5 KiB
C
/*
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*
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* @par
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* IXP400 SW Release version 2.0
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*
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* -- Copyright Notice --
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*
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* @par
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* Copyright 2001-2005, Intel Corporation.
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* All rights reserved.
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*
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* @par
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @par
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* -- End of Copyright Notice --
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*/
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#ifndef IxEthAccMac_p_H
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#define IxEthAccMac_p_H
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#include "IxOsal.h"
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#define IX_ETH_ACC_MAX_MULTICAST_ADDRESSES 256
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#define IX_ETH_ACC_NUM_PORTS 3
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#define IX_ETH_ACC_MAX_FRAME_SIZE_DEFAULT 1536
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#define IX_ETH_ACC_MAX_FRAME_SIZE_UPPER_RANGE (65536-64)
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#define IX_ETH_ACC_MAX_FRAME_SIZE_LOWER_RANGE 64
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/*
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*
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* MAC register definitions
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*
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*/
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#define IX_ETH_ACC_MAC_0_BASE IX_OSAL_IXP400_ETHA_PHYS_BASE
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#define IX_ETH_ACC_MAC_1_BASE IX_OSAL_IXP400_ETHB_PHYS_BASE
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#define IX_ETH_ACC_MAC_2_BASE IX_OSAL_IXP400_ETH_NPEA_PHYS_BASE
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#define IX_ETH_ACC_MAC_TX_CNTRL1 0x000
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#define IX_ETH_ACC_MAC_TX_CNTRL2 0x004
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#define IX_ETH_ACC_MAC_RX_CNTRL1 0x010
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#define IX_ETH_ACC_MAC_RX_CNTRL2 0x014
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#define IX_ETH_ACC_MAC_RANDOM_SEED 0x020
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#define IX_ETH_ACC_MAC_THRESH_P_EMPTY 0x030
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#define IX_ETH_ACC_MAC_THRESH_P_FULL 0x038
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#define IX_ETH_ACC_MAC_BUF_SIZE_TX 0x040
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#define IX_ETH_ACC_MAC_TX_DEFER 0x050
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#define IX_ETH_ACC_MAC_RX_DEFER 0x054
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#define IX_ETH_ACC_MAC_TX_TWO_DEFER_1 0x060
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#define IX_ETH_ACC_MAC_TX_TWO_DEFER_2 0x064
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#define IX_ETH_ACC_MAC_SLOT_TIME 0x070
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#define IX_ETH_ACC_MAC_MDIO_CMD_1 0x080
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#define IX_ETH_ACC_MAC_MDIO_CMD_2 0x084
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#define IX_ETH_ACC_MAC_MDIO_CMD_3 0x088
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#define IX_ETH_ACC_MAC_MDIO_CMD_4 0x08c
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#define IX_ETH_ACC_MAC_MDIO_STS_1 0x090
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#define IX_ETH_ACC_MAC_MDIO_STS_2 0x094
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#define IX_ETH_ACC_MAC_MDIO_STS_3 0x098
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#define IX_ETH_ACC_MAC_MDIO_STS_4 0x09c
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#define IX_ETH_ACC_MAC_ADDR_MASK_1 0x0A0
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#define IX_ETH_ACC_MAC_ADDR_MASK_2 0x0A4
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#define IX_ETH_ACC_MAC_ADDR_MASK_3 0x0A8
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#define IX_ETH_ACC_MAC_ADDR_MASK_4 0x0AC
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#define IX_ETH_ACC_MAC_ADDR_MASK_5 0x0B0
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#define IX_ETH_ACC_MAC_ADDR_MASK_6 0x0B4
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#define IX_ETH_ACC_MAC_ADDR_1 0x0C0
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#define IX_ETH_ACC_MAC_ADDR_2 0x0C4
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#define IX_ETH_ACC_MAC_ADDR_3 0x0C8
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#define IX_ETH_ACC_MAC_ADDR_4 0x0CC
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#define IX_ETH_ACC_MAC_ADDR_5 0x0D0
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#define IX_ETH_ACC_MAC_ADDR_6 0x0D4
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#define IX_ETH_ACC_MAC_INT_CLK_THRESH 0x0E0
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#define IX_ETH_ACC_MAC_UNI_ADDR_1 0x0F0
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#define IX_ETH_ACC_MAC_UNI_ADDR_2 0x0F4
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#define IX_ETH_ACC_MAC_UNI_ADDR_3 0x0F8
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#define IX_ETH_ACC_MAC_UNI_ADDR_4 0x0FC
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#define IX_ETH_ACC_MAC_UNI_ADDR_5 0x100
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#define IX_ETH_ACC_MAC_UNI_ADDR_6 0x104
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#define IX_ETH_ACC_MAC_CORE_CNTRL 0x1FC
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/*
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*
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*Bit definitions
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*
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*/
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/* TX Control Register 1*/
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#define IX_ETH_ACC_TX_CNTRL1_TX_EN BIT(0)
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#define IX_ETH_ACC_TX_CNTRL1_DUPLEX BIT(1)
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#define IX_ETH_ACC_TX_CNTRL1_RETRY BIT(2)
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#define IX_ETH_ACC_TX_CNTRL1_PAD_EN BIT(3)
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#define IX_ETH_ACC_TX_CNTRL1_FCS_EN BIT(4)
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#define IX_ETH_ACC_TX_CNTRL1_2DEFER BIT(5)
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#define IX_ETH_ACC_TX_CNTRL1_RMII BIT(6)
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/* TX Control Register 2 */
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#define IX_ETH_ACC_TX_CNTRL2_RETRIES_MASK 0xf
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/* RX Control Register 1 */
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#define IX_ETH_ACC_RX_CNTRL1_RX_EN BIT(0)
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#define IX_ETH_ACC_RX_CNTRL1_PADSTRIP_EN BIT(1)
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#define IX_ETH_ACC_RX_CNTRL1_CRC_EN BIT(2)
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#define IX_ETH_ACC_RX_CNTRL1_PAUSE_EN BIT(3)
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#define IX_ETH_ACC_RX_CNTRL1_LOOP_EN BIT(4)
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#define IX_ETH_ACC_RX_CNTRL1_ADDR_FLTR_EN BIT(5)
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#define IX_ETH_ACC_RX_CNTRL1_RX_RUNT_EN BIT(6)
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#define IX_ETH_ACC_RX_CNTRL1_BCAST_DIS BIT(7)
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/* RX Control Register 2 */
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#define IX_ETH_ACC_RX_CNTRL2_DEFER_EN BIT(0)
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/* Core Control Register */
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#define IX_ETH_ACC_CORE_RESET BIT(0)
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#define IX_ETH_ACC_CORE_RX_FIFO_FLUSH BIT(1)
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#define IX_ETH_ACC_CORE_TX_FIFO_FLUSH BIT(2)
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#define IX_ETH_ACC_CORE_SEND_JAM BIT(3)
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#define IX_ETH_ACC_CORE_MDC_EN BIT(4)
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/* 1st bit of 1st MAC octet */
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#define IX_ETH_ACC_ETH_MAC_BCAST_MCAST_BIT ( 1)
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/*
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*
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* Default values
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*
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*/
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#define IX_ETH_ACC_TX_CNTRL1_DEFAULT (IX_ETH_ACC_TX_CNTRL1_TX_EN | \
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IX_ETH_ACC_TX_CNTRL1_RETRY | \
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IX_ETH_ACC_TX_CNTRL1_FCS_EN | \
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IX_ETH_ACC_TX_CNTRL1_2DEFER | \
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IX_ETH_ACC_TX_CNTRL1_PAD_EN)
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#define IX_ETH_ACC_TX_MAX_RETRIES_DEFAULT 0x0f
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#define IX_ETH_ACC_RX_CNTRL1_DEFAULT (IX_ETH_ACC_RX_CNTRL1_CRC_EN \
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| IX_ETH_ACC_RX_CNTRL1_RX_EN)
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#define IX_ETH_ACC_RX_CNTRL2_DEFAULT 0x0
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/* Thresholds determined by NPE firmware FS */
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#define IX_ETH_ACC_MAC_THRESH_P_EMPTY_DEFAULT 0x12
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#define IX_ETH_ACC_MAC_THRESH_P_FULL_DEFAULT 0x30
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/* Number of bytes that must be in the tx fifo before
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transmission commences*/
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#define IX_ETH_ACC_MAC_BUF_SIZE_TX_DEFAULT 0x8
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/* One-part deferral values */
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#define IX_ETH_ACC_MAC_TX_DEFER_DEFAULT 0x15
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#define IX_ETH_ACC_MAC_RX_DEFER_DEFAULT 0x16
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/* Two-part deferral values... */
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#define IX_ETH_ACC_MAC_TX_TWO_DEFER_1_DEFAULT 0x08
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#define IX_ETH_ACC_MAC_TX_TWO_DEFER_2_DEFAULT 0x07
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/* This value applies to MII */
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#define IX_ETH_ACC_MAC_SLOT_TIME_DEFAULT 0x80
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/* This value applies to RMII */
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#define IX_ETH_ACC_MAC_SLOT_TIME_RMII_DEFAULT 0xFF
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#define IX_ETH_ACC_MAC_ADDR_MASK_DEFAULT 0xFF
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#define IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT 0x1
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/*The following is a value chosen at random*/
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#define IX_ETH_ACC_RANDOM_SEED_DEFAULT 0x8
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/*By default we must configure the MAC to generate the
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MDC clock*/
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#define IX_ETH_ACC_CORE_DEFAULT (IX_ETH_ACC_CORE_MDC_EN)
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#define IXP425_ETH_ACC_MAX_PHY 2
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#define IXP425_ETH_ACC_MAX_AN_ENTRIES 20
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#define IX_ETH_ACC_MAC_RESET_DELAY 1
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#define IX_ETH_ACC_MAC_ALL_BITS_SET 0xFF
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#define IX_ETH_ACC_MAC_MSGID_SHL 24
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#define IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS 20
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#define IX_ETH_ACC_PORT_DISABLE_DELAY_COUNT 200 /* 4 seconds timeout */
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#define IX_ETH_ACC_PORT_DISABLE_RETRY_COUNT 3
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#define IX_ETH_ACC_MIB_STATS_DELAY_MSECS 2000 /* 2 seconds delay for ethernet stats */
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/*Register access macros*/
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#if (CPU == SIMSPARCSOLARIS)
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extern void registerWriteStub (UINT32 base, UINT32 offset, UINT32 val);
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extern UINT32 registerReadStub (UINT32 base, UINT32 offset);
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#define REG_WRITE(b,o,v) registerWriteStub(b, o, v)
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#define REG_READ(b,o,v) do { v = registerReadStub(b, o); } while (0)
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#else
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#define REG_WRITE(b,o,v) IX_OSAL_WRITE_LONG((volatile UINT32 *)(b + o), v)
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#define REG_READ(b,o,v) (v = IX_OSAL_READ_LONG((volatile UINT32 *)(b + o)))
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#endif
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void ixEthAccMacUnload(void);
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IxEthAccStatus ixEthAccMacMemInit(void);
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/* MAC core loopback */
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IxEthAccStatus ixEthAccPortLoopbackEnable(IxEthAccPortId portId);
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IxEthAccStatus ixEthAccPortLoopbackDisable(IxEthAccPortId portId);
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/* MAC core traffic control */
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IxEthAccStatus ixEthAccPortTxEnablePriv(IxEthAccPortId portId);
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IxEthAccStatus ixEthAccPortTxDisablePriv(IxEthAccPortId portId);
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IxEthAccStatus ixEthAccPortRxEnablePriv(IxEthAccPortId portId);
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IxEthAccStatus ixEthAccPortRxDisablePriv(IxEthAccPortId portId);
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IxEthAccStatus ixEthAccPortMacResetPriv(IxEthAccPortId portId);
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/* NPE software loopback */
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IxEthAccStatus ixEthAccNpeLoopbackDisablePriv(IxEthAccPortId portId);
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IxEthAccStatus ixEthAccNpeLoopbackEnablePriv(IxEthAccPortId portId);
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#endif /*IxEthAccMac_p_H*/
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