mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-28 15:41:40 +00:00
493c03f820
Add PCIe device rtl8169 net adapter driver support. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
113 lines
3 KiB
Text
113 lines
3 KiB
Text
CONFIG_RISCV=y
|
|
CONFIG_SYS_MALLOC_LEN=0x800000
|
|
CONFIG_SYS_MALLOC_F_LEN=0x10000
|
|
CONFIG_SPL_GPIO=y
|
|
CONFIG_NR_DRAM_BANKS=1
|
|
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
|
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80000000
|
|
CONFIG_SF_DEFAULT_SPEED=100000000
|
|
CONFIG_SPL_DM_SPI=y
|
|
CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2"
|
|
CONFIG_SPL_TEXT_BASE=0x8000000
|
|
CONFIG_SYS_PROMPT="StarFive # "
|
|
CONFIG_OF_LIBFDT_OVERLAY=y
|
|
CONFIG_DM_RESET=y
|
|
CONFIG_SPL_MMC=y
|
|
CONFIG_SPL_DRIVERS_MISC=y
|
|
CONFIG_SPL_STACK=0x8180000
|
|
CONFIG_SPL=y
|
|
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
|
CONFIG_SPL_SPI=y
|
|
CONFIG_SYS_LOAD_ADDR=0x82000000
|
|
CONFIG_SYS_PCI_64BIT=y
|
|
CONFIG_PCI=y
|
|
CONFIG_TARGET_STARFIVE_VISIONFIVE2=y
|
|
CONFIG_SPL_OPENSBI_LOAD_ADDR=0x40000000
|
|
CONFIG_ARCH_RV64I=y
|
|
CONFIG_CMODEL_MEDANY=y
|
|
CONFIG_RISCV_SMODE=y
|
|
# CONFIG_OF_BOARD_FIXUP is not set
|
|
CONFIG_FIT=y
|
|
CONFIG_DISTRO_DEFAULTS=y
|
|
CONFIG_QSPI_BOOT=y
|
|
CONFIG_SD_BOOT=y
|
|
CONFIG_USE_BOOTARGS=y
|
|
CONFIG_BOOTARGS="console=ttyS0,115200 debug rootwait earlycon=sbi"
|
|
CONFIG_USE_PREBOOT=y
|
|
CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr ${fdtcontroladdr};"
|
|
CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2.dtb"
|
|
CONFIG_DISPLAY_CPUINFO=y
|
|
CONFIG_DISPLAY_BOARDINFO=y
|
|
CONFIG_ID_EEPROM=y
|
|
CONFIG_SYS_EEPROM_BUS_NUM=5
|
|
CONFIG_SPL_MAX_SIZE=0x40000
|
|
CONFIG_SPL_PAD_TO=0x0
|
|
CONFIG_SPL_BSS_START_ADDR=0x8040000
|
|
CONFIG_SPL_BSS_MAX_SIZE=0x10000
|
|
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
|
CONFIG_SYS_SPL_MALLOC=y
|
|
CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
|
|
CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80000000
|
|
CONFIG_SYS_SPL_MALLOC_SIZE=0x400000
|
|
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
|
|
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2
|
|
CONFIG_SPL_I2C=y
|
|
CONFIG_SPL_DM_SPI_FLASH=y
|
|
CONFIG_SPL_DM_RESET=y
|
|
CONFIG_SPL_SPI_LOAD=y
|
|
CONFIG_SYS_CBSIZE=256
|
|
CONFIG_SYS_PBSIZE=276
|
|
CONFIG_SYS_BOOTM_LEN=0x4000000
|
|
CONFIG_CMD_EEPROM=y
|
|
CONFIG_SYS_EEPROM_SIZE=512
|
|
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
|
|
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
|
|
CONFIG_CMD_MEMINFO=y
|
|
CONFIG_CMD_I2C=y
|
|
CONFIG_CMD_PCI=y
|
|
CONFIG_CMD_TFTPPUT=y
|
|
CONFIG_OF_BOARD=y
|
|
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
|
CONFIG_SPL_DM_SEQ_ALIAS=y
|
|
CONFIG_REGMAP=y
|
|
CONFIG_SYSCON=y
|
|
CONFIG_SPL_CLK_COMPOSITE_CCF=y
|
|
CONFIG_CLK_COMPOSITE_CCF=y
|
|
CONFIG_SPL_CLK_JH7110=y
|
|
CONFIG_DM_I2C=y
|
|
CONFIG_SYS_I2C_DW=y
|
|
CONFIG_MISC=y
|
|
CONFIG_I2C_EEPROM=y
|
|
CONFIG_SPL_I2C_EEPROM=y
|
|
CONFIG_SYS_I2C_EEPROM_ADDR=0X50
|
|
CONFIG_MMC_HS400_SUPPORT=y
|
|
CONFIG_SPL_MMC_HS400_SUPPORT=y
|
|
CONFIG_MMC_DW=y
|
|
CONFIG_MMC_DW_SNPS=y
|
|
CONFIG_SPI_FLASH_EON=y
|
|
CONFIG_SPI_FLASH_GIGADEVICE=y
|
|
CONFIG_SPI_FLASH_ISSI=y
|
|
CONFIG_SPI_FLASH_MACRONIX=y
|
|
CONFIG_PHY_MOTORCOMM=y
|
|
CONFIG_DM_MDIO=y
|
|
CONFIG_DM_ETH_PHY=y
|
|
CONFIG_DWC_ETH_QOS=y
|
|
CONFIG_DWC_ETH_QOS_STARFIVE=y
|
|
CONFIG_RGMII=y
|
|
CONFIG_RMII=y
|
|
CONFIG_RTL8169=y
|
|
CONFIG_NVME_PCI=y
|
|
CONFIG_DM_PCI_COMPAT=y
|
|
CONFIG_PCI_REGION_MULTI_ENTRY=y
|
|
CONFIG_PCIE_STARFIVE_JH7110=y
|
|
CONFIG_PINCTRL=y
|
|
CONFIG_PINCONF=y
|
|
CONFIG_SPL_PINCTRL=y
|
|
CONFIG_SPL_PINCONF=y
|
|
CONFIG_SPL_PINCTRL_STARFIVE=y
|
|
CONFIG_SPL_PINCTRL_STARFIVE_JH7110=y
|
|
CONFIG_PINCTRL_STARFIVE=y
|
|
# CONFIG_RAM_SIFIVE is not set
|
|
CONFIG_SYS_NS16550=y
|
|
CONFIG_CADENCE_QSPI=y
|
|
CONFIG_TIMER_EARLY=y
|