Bin Meng 9675d92027 riscv: Rename SiFive CLINT to RISC-V ALINT ... As the RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V ALINT in the source tree to be future-proof. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>		2023-07-12 13:21:40 +08:00
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cpu.c	riscv: cpu: fu540: Add support for cpu fu540	2020-06-04 09:44:09 +08:00
dram.c	board_f: Fix types for board_get_usable_ram_top()	2022-09-23 15:12:42 -04:00
Kconfig	riscv: Rename SiFive CLINT to RISC-V ALINT	2023-07-12 13:21:40 +08:00
Makefile	board: sifive: use ccache driver instead of helper function	2021-09-07 10:34:29 +08:00
spl.c	Revert "riscv: cpu: fu740: clear feature disable CSR"	2021-05-14 16:26:20 +08:00