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u-boot/arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi
Paweł Anikiel e21b8ac3f1 arm: dts: Add Mercury+ AA1 devicetrees
Devicetree headers for Mercury+ AA1 module

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-07-01 14:57:13 +08:00

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2022 Google LLC
*/
#include "socfpga_arria10.dtsi"
/ {
aliases {
ethernet0 = &gmac0;
serial1 = &uart1;
};
chosen {
stdout-path = "serial1:115200n8";
};
memory@0 {
name = "memory";
device_type = "memory";
reg = <0x0 0x80000000>; /* 2GB */
};
};
&gmac0 {
phy-mode = "rgmii";
phy-handle = <&phy3>;
max-frame-size = <3800>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy3: ethernet-phy@3 {
reg = <3>;
txd0-skew-ps = <0>; /* -420ps */
txd1-skew-ps = <0>; /* -420ps */
txd2-skew-ps = <0>; /* -420ps */
txd3-skew-ps = <0>; /* -420ps */
rxd0-skew-ps = <420>; /* 0ps */
rxd1-skew-ps = <420>; /* 0ps */
rxd2-skew-ps = <420>; /* 0ps */
rxd3-skew-ps = <420>; /* 0ps */
txen-skew-ps = <0>; /* -420ps */
txc-skew-ps = <1860>; /* 960ps */
rxdv-skew-ps = <420>; /* 0ps */
rxc-skew-ps = <1680>; /* 780ps */
};
};
};
&i2c1 {
atsha204a: atsha204a@64 {
compatible = "atmel,atsha204a";
reg = <0x64>;
};
isl12022: isl12022@6f {
compatible = "isil,isl12022";
reg = <0x6f>;
};
};
&mmc {
cap-sd-highspeed;
broken-cd;
bus-width = <4>;
};
&osc1 {
clock-frequency = <33330000>;
};