mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-12 07:57:21 +00:00
b5e01eecc8
GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH). Adding details for the same. Below is the brief description of DDR3 init sequence(SW leveling): -> Enable VTT regulator -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program leveling registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
28 lines
682 B
C
28 lines
682 B
C
/*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
#ifndef _GPIO_AM33xx_H
|
|
#define _GPIO_AM33xx_H
|
|
|
|
#include <asm/omap_gpio.h>
|
|
|
|
#define OMAP_MAX_GPIO 128
|
|
|
|
#define AM33XX_GPIO0_BASE 0x44E07000
|
|
#define AM33XX_GPIO1_BASE 0x4804C000
|
|
#define AM33XX_GPIO2_BASE 0x481AC000
|
|
#define AM33XX_GPIO3_BASE 0x481AE000
|
|
|
|
#define GPIO_22 22
|
|
|
|
/* GPIO CTRL register */
|
|
#define GPIO_CTRL_DISABLEMODULE_SHIFT 0
|
|
#define GPIO_CTRL_DISABLEMODULE_MASK (1 << 0)
|
|
#define GPIO_CTRL_ENABLEMODULE GPIO_CTRL_DISABLEMODULE_MASK
|
|
|
|
/* GPIO OUTPUT ENABLE register */
|
|
#define GPIO_OE_ENABLE(x) (1 << x)
|
|
|
|
/* GPIO SETDATAOUT register */
|
|
#define GPIO_SETDATAOUT(x) (1 << x)
|
|
#endif /* _GPIO_AM33xx_H */
|