mirror of
https://github.com/AsahiLinux/u-boot
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74 lines
2.1 KiB
C
74 lines
2.1 KiB
C
/*
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* U-boot - ezkit561.c
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*
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* Copyright (c) 2005 Bas Vermeulen <bas@buyways.nl>
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* Copyright (c) 2005-2007 Analog Devices Inc.
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*
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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int checkboard(void)
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{
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printf("CPU: ADSP BF561\n");
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printf("Board: ADI BF561 EZ-Kit Lite board\n");
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printf(" Support: http://blackfin.uclinux.org/\n");
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return 0;
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}
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long int initdram(int board_type)
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{
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#ifdef DEBUG
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int brate;
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char *tmp = getenv("baudrate");
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brate = simple_strtoul(tmp, NULL, 16);
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printf("Serial Port initialized with Baud rate = %x\n", brate);
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printf("SDRAM attributes:\n");
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printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles"
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"tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n",
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3, 3, 6, 2, 3);
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printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
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printf("Bank size = %d MB\n", CFG_MAX_RAM_SIZE >> 20);
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#endif
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gd->bd->bi_memstart = CFG_SDRAM_BASE;
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gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
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return CFG_MAX_RAM_SIZE;
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}
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#if defined(CONFIG_MISC_INIT_R)
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/* miscellaneous platform dependent initialisations */
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int misc_init_r(void)
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{
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/* Keep PF12 low to be able to drive the USB-LAN Extender */
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*pFIO0_DIR = 0x0000;
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*pFIO0_FLAG_C = 0x1000; /* Clear PF12 */
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sync();
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*pFIO0_POLAR = 0x0000;
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sync();
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return 0;
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}
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#endif
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