mirror of
https://github.com/AsahiLinux/u-boot
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69b19ca67b
Sync k3-j721e DTS with kernel.org v6.6-rc1. * Use mcu_timer0 defined in k3-j721e-mcu-wakeup.dtsi and remove timer0, we have its clocks set up in clk-data now * Remove hbmc node as support is buggy and needs to be fixed * Remove aliases and chosen node, use them from Kernel * Remove /delete-property/ and clock-frequency from sdhci, usbss, and mcu_uart nodes as we have them in clk and dev data * Remove dummy_clocks as they are not needed * Remove cpsw node as it is not required since it has been fixed in U-Boot * Remove pcie nodes, they are not needed * Remove mcu_i2c0 as it is used for tps659413 PMIC in j721e-sk for which support is not yet added * Change secproxy nodes to their Linux definitions * Remove overriding of ti,cluster-mode in MAIN R5 to default to lockstep mode same as Kernel * Retain tps6594 node as TPS6594 PMIC support is still under review in the Kernel [1], cleanup will be taken post its merge [1] https://lore.kernel.org/all/20230810-tps6594-v6-0-2b2e2399e2ef@ti.com/ Signed-off-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
674 lines
18 KiB
Text
674 lines
18 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals
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*
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* Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
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*/
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&cbass_mcu_wakeup {
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dmsc: system-controller@44083000 {
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compatible = "ti,k2g-sci";
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ti,host-id = <12>;
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mbox-names = "rx", "tx";
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mboxes = <&secure_proxy_main 11>,
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<&secure_proxy_main 13>;
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reg-names = "debug_messages";
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reg = <0x00 0x44083000 0x0 0x1000>;
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k3_pds: power-controller {
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compatible = "ti,sci-pm-domain";
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#power-domain-cells = <2>;
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};
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k3_clks: clock-controller {
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compatible = "ti,k2g-sci-clk";
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#clock-cells = <2>;
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};
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k3_reset: reset-controller {
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compatible = "ti,sci-reset";
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#reset-cells = <2>;
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};
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};
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mcu_conf: syscon@40f00000 {
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compatible = "syscon", "simple-mfd";
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reg = <0x0 0x40f00000 0x0 0x20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x40f00000 0x20000>;
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phy_gmii_sel: phy@4040 {
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compatible = "ti,am654-phy-gmii-sel";
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reg = <0x4040 0x4>;
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#phy-cells = <1>;
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};
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};
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chipid@43000014 {
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compatible = "ti,am654-chipid";
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reg = <0x0 0x43000014 0x0 0x4>;
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};
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wkup_pmx0: pinctrl@4301c000 {
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compatible = "pinctrl-single";
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/* Proxy 0 addressing */
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reg = <0x00 0x4301c000 0x00 0x178>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0xffffffff>;
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};
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/* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
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mcu_timerio_input: pinctrl@40f04200 {
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compatible = "pinctrl-single";
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reg = <0x00 0x40f04200 0x00 0x28>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0x0000000f>;
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/* Non-MPU Firmware usage */
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status = "reserved";
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};
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/* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
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mcu_timerio_output: pinctrl@40f04280 {
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compatible = "pinctrl-single";
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reg = <0x00 0x40f04280 0x00 0x28>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0x0000000f>;
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/* Non-MPU Firmware usage */
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status = "reserved";
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};
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mcu_ram: sram@41c00000 {
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compatible = "mmio-sram";
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reg = <0x00 0x41c00000 0x00 0x100000>;
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ranges = <0x0 0x00 0x41c00000 0x100000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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mcu_timer0: timer@40400000 {
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compatible = "ti,am654-timer";
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reg = <0x00 0x40400000 0x00 0x400>;
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interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&k3_clks 35 1>;
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clock-names = "fck";
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assigned-clocks = <&k3_clks 35 1>;
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assigned-clock-parents = <&k3_clks 35 2>;
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power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
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ti,timer-pwm;
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/* Non-MPU Firmware usage */
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status = "reserved";
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};
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mcu_timer1: timer@40410000 {
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compatible = "ti,am654-timer";
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reg = <0x00 0x40410000 0x00 0x400>;
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interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&k3_clks 71 1>;
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clock-names = "fck";
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assigned-clocks = <&k3_clks 71 1>, <&k3_clks 322 0>;
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assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 322 1>;
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power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>;
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ti,timer-pwm;
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/* Non-MPU Firmware usage */
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status = "reserved";
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};
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mcu_timer2: timer@40420000 {
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compatible = "ti,am654-timer";
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reg = <0x00 0x40420000 0x00 0x400>;
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interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&k3_clks 72 1>;
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clock-names = "fck";
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assigned-clocks = <&k3_clks 72 1>;
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assigned-clock-parents = <&k3_clks 72 2>;
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power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
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ti,timer-pwm;
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/* Non-MPU Firmware usage */
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status = "reserved";
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};
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mcu_timer3: timer@40430000 {
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compatible = "ti,am654-timer";
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reg = <0x00 0x40430000 0x00 0x400>;
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interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&k3_clks 73 1>;
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clock-names = "fck";
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assigned-clocks = <&k3_clks 73 1>, <&k3_clks 323 0>;
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assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 323 1>;
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power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
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ti,timer-pwm;
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/* Non-MPU Firmware usage */
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status = "reserved";
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};
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mcu_timer4: timer@40440000 {
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compatible = "ti,am654-timer";
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reg = <0x00 0x40440000 0x00 0x400>;
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interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&k3_clks 74 1>;
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clock-names = "fck";
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assigned-clocks = <&k3_clks 74 1>;
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assigned-clock-parents = <&k3_clks 74 2>;
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power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
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ti,timer-pwm;
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/* Non-MPU Firmware usage */
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status = "reserved";
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};
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mcu_timer5: timer@40450000 {
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compatible = "ti,am654-timer";
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reg = <0x00 0x40450000 0x00 0x400>;
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interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&k3_clks 75 1>;
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clock-names = "fck";
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assigned-clocks = <&k3_clks 75 1>, <&k3_clks 324 0>;
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assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 324 1>;
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power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
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ti,timer-pwm;
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/* Non-MPU Firmware usage */
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status = "reserved";
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};
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mcu_timer6: timer@40460000 {
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compatible = "ti,am654-timer";
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reg = <0x00 0x40460000 0x00 0x400>;
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interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&k3_clks 76 1>;
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clock-names = "fck";
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assigned-clocks = <&k3_clks 76 1>;
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assigned-clock-parents = <&k3_clks 76 2>;
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power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>;
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ti,timer-pwm;
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/* Non-MPU Firmware usage */
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status = "reserved";
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};
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mcu_timer7: timer@40470000 {
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compatible = "ti,am654-timer";
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reg = <0x00 0x40470000 0x00 0x400>;
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interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&k3_clks 77 1>;
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clock-names = "fck";
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assigned-clocks = <&k3_clks 77 1>, <&k3_clks 325 0>;
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assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 325 1>;
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power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
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ti,timer-pwm;
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/* Non-MPU Firmware usage */
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status = "reserved";
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};
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mcu_timer8: timer@40480000 {
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compatible = "ti,am654-timer";
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reg = <0x00 0x40480000 0x00 0x400>;
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interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&k3_clks 78 1>;
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clock-names = "fck";
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assigned-clocks = <&k3_clks 78 1>;
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assigned-clock-parents = <&k3_clks 78 2>;
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power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
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ti,timer-pwm;
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/* Non-MPU Firmware usage */
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status = "reserved";
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};
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mcu_timer9: timer@40490000 {
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compatible = "ti,am654-timer";
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reg = <0x00 0x40490000 0x00 0x400>;
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interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&k3_clks 79 1>;
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clock-names = "fck";
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assigned-clocks = <&k3_clks 79 1>, <&k3_clks 326 0>;
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assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 326 1>;
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power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
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ti,timer-pwm;
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/* Non-MPU Firmware usage */
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status = "reserved";
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};
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wkup_uart0: serial@42300000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x42300000 0x00 0x100>;
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interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 287 0>;
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clock-names = "fclk";
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status = "disabled";
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};
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mcu_uart0: serial@40a00000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x40a00000 0x00 0x100>;
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interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <96000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 149 0>;
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clock-names = "fclk";
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status = "disabled";
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};
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wkup_gpio_intr: interrupt-controller@42200000 {
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compatible = "ti,sci-intr";
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reg = <0x00 0x42200000 0x00 0x400>;
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ti,intr-trigger-type = <1>;
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interrupt-controller;
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interrupt-parent = <&gic500>;
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#interrupt-cells = <1>;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <137>;
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ti,interrupt-ranges = <16 960 16>;
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};
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wkup_gpio0: gpio@42110000 {
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compatible = "ti,j721e-gpio", "ti,keystone-gpio";
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reg = <0x0 0x42110000 0x0 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&wkup_gpio_intr>;
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interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ti,ngpio = <84>;
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ti,davinci-gpio-unbanked = <0>;
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power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 113 0>;
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clock-names = "gpio";
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status = "disabled";
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};
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wkup_gpio1: gpio@42100000 {
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compatible = "ti,j721e-gpio", "ti,keystone-gpio";
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reg = <0x0 0x42100000 0x0 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&wkup_gpio_intr>;
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interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ti,ngpio = <84>;
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ti,davinci-gpio-unbanked = <0>;
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power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 114 0>;
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clock-names = "gpio";
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status = "disabled";
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};
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mcu_i2c0: i2c@40b00000 {
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compatible = "ti,j721e-i2c", "ti,omap4-i2c";
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reg = <0x0 0x40b00000 0x0 0x100>;
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interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "fck";
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clocks = <&k3_clks 194 0>;
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power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
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status = "disabled";
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};
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mcu_i2c1: i2c@40b10000 {
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compatible = "ti,j721e-i2c", "ti,omap4-i2c";
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reg = <0x0 0x40b10000 0x0 0x100>;
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interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "fck";
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clocks = <&k3_clks 195 0>;
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power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
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status = "disabled";
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};
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wkup_i2c0: i2c@42120000 {
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compatible = "ti,j721e-i2c", "ti,omap4-i2c";
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reg = <0x0 0x42120000 0x0 0x100>;
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interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "fck";
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clocks = <&k3_clks 197 0>;
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power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
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status = "disabled";
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};
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fss: bus@47000000 {
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compatible = "simple-bus";
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reg = <0x0 0x47000000 0x0 0x100>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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hbmc_mux: mux-controller@47000004 {
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compatible = "reg-mux";
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reg = <0x00 0x47000004 0x00 0x2>;
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#mux-control-cells = <1>;
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mux-reg-masks = <0x4 0x2>; /* HBMC select */
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};
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hbmc: hyperbus@47034000 {
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compatible = "ti,am654-hbmc";
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reg = <0x00 0x47034000 0x00 0x100>,
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<0x05 0x00000000 0x01 0x0000000>;
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power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 102 0>;
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assigned-clocks = <&k3_clks 102 5>;
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assigned-clock-rates = <333333333>;
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#address-cells = <2>;
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#size-cells = <1>;
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mux-controls = <&hbmc_mux 0>;
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status = "disabled";
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};
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ospi0: spi@47040000 {
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compatible = "ti,am654-ospi", "cdns,qspi-nor";
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reg = <0x0 0x47040000 0x0 0x100>,
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<0x5 0x00000000 0x1 0x0000000>;
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interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
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cdns,fifo-depth = <256>;
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cdns,fifo-width = <4>;
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cdns,trigger-address = <0x0>;
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clocks = <&k3_clks 103 0>;
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assigned-clocks = <&k3_clks 103 0>;
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assigned-clock-parents = <&k3_clks 103 2>;
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assigned-clock-rates = <166666666>;
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power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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ospi1: spi@47050000 {
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compatible = "ti,am654-ospi", "cdns,qspi-nor";
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reg = <0x0 0x47050000 0x0 0x100>,
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<0x7 0x00000000 0x1 0x00000000>;
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interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
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cdns,fifo-depth = <256>;
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cdns,fifo-width = <4>;
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cdns,trigger-address = <0x0>;
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clocks = <&k3_clks 104 0>;
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power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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tscadc0: tscadc@40200000 {
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compatible = "ti,am3359-tscadc";
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reg = <0x0 0x40200000 0x0 0x1000>;
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interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 0 1>;
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assigned-clocks = <&k3_clks 0 3>;
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assigned-clock-rates = <60000000>;
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clock-names = "fck";
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dmas = <&main_udmap 0x7400>,
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<&main_udmap 0x7401>;
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dma-names = "fifo0", "fifo1";
|
|
status = "disabled";
|
|
|
|
adc {
|
|
#io-channel-cells = <1>;
|
|
compatible = "ti,am3359-adc";
|
|
};
|
|
};
|
|
|
|
tscadc1: tscadc@40210000 {
|
|
compatible = "ti,am3359-tscadc";
|
|
reg = <0x0 0x40210000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>;
|
|
clocks = <&k3_clks 1 1>;
|
|
assigned-clocks = <&k3_clks 1 3>;
|
|
assigned-clock-rates = <60000000>;
|
|
clock-names = "fck";
|
|
dmas = <&main_udmap 0x7402>,
|
|
<&main_udmap 0x7403>;
|
|
dma-names = "fifo0", "fifo1";
|
|
status = "disabled";
|
|
|
|
adc {
|
|
#io-channel-cells = <1>;
|
|
compatible = "ti,am3359-adc";
|
|
};
|
|
};
|
|
|
|
mcu_navss: bus@28380000 {
|
|
compatible = "simple-mfd";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
|
|
dma-coherent;
|
|
dma-ranges;
|
|
|
|
ti,sci-dev-id = <232>;
|
|
|
|
mcu_ringacc: ringacc@2b800000 {
|
|
compatible = "ti,am654-navss-ringacc";
|
|
reg = <0x0 0x2b800000 0x0 0x400000>,
|
|
<0x0 0x2b000000 0x0 0x400000>,
|
|
<0x0 0x28590000 0x0 0x100>,
|
|
<0x0 0x2a500000 0x0 0x40000>,
|
|
<0x0 0x28440000 0x0 0x40000>;
|
|
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
|
|
ti,num-rings = <286>;
|
|
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
|
|
ti,sci = <&dmsc>;
|
|
ti,sci-dev-id = <235>;
|
|
msi-parent = <&main_udmass_inta>;
|
|
};
|
|
|
|
mcu_udmap: dma-controller@285c0000 {
|
|
compatible = "ti,j721e-navss-mcu-udmap";
|
|
reg = <0x0 0x285c0000 0x0 0x100>,
|
|
<0x0 0x2a800000 0x0 0x40000>,
|
|
<0x0 0x2aa00000 0x0 0x40000>;
|
|
reg-names = "gcfg", "rchanrt", "tchanrt";
|
|
msi-parent = <&main_udmass_inta>;
|
|
#dma-cells = <1>;
|
|
|
|
ti,sci = <&dmsc>;
|
|
ti,sci-dev-id = <236>;
|
|
ti,ringacc = <&mcu_ringacc>;
|
|
|
|
ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
|
|
<0x0f>; /* TX_HCHAN */
|
|
ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
|
|
<0x0b>; /* RX_HCHAN */
|
|
ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
|
|
};
|
|
};
|
|
|
|
secure_proxy_mcu: mailbox@2a480000 {
|
|
compatible = "ti,am654-secure-proxy";
|
|
#mbox-cells = <1>;
|
|
reg-names = "target_data", "rt", "scfg";
|
|
reg = <0x0 0x2a480000 0x0 0x80000>,
|
|
<0x0 0x2a380000 0x0 0x80000>,
|
|
<0x0 0x2a400000 0x0 0x80000>;
|
|
/*
|
|
* Marked Disabled:
|
|
* Node is incomplete as it is meant for bootloaders and
|
|
* firmware on non-MPU processors
|
|
*/
|
|
status = "disabled";
|
|
};
|
|
|
|
mcu_cpsw: ethernet@46000000 {
|
|
compatible = "ti,j721e-cpsw-nuss";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
reg = <0x0 0x46000000 0x0 0x200000>;
|
|
reg-names = "cpsw_nuss";
|
|
ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
|
|
dma-coherent;
|
|
clocks = <&k3_clks 18 22>;
|
|
clock-names = "fck";
|
|
power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
dmas = <&mcu_udmap 0xf000>,
|
|
<&mcu_udmap 0xf001>,
|
|
<&mcu_udmap 0xf002>,
|
|
<&mcu_udmap 0xf003>,
|
|
<&mcu_udmap 0xf004>,
|
|
<&mcu_udmap 0xf005>,
|
|
<&mcu_udmap 0xf006>,
|
|
<&mcu_udmap 0xf007>,
|
|
<&mcu_udmap 0x7000>;
|
|
dma-names = "tx0", "tx1", "tx2", "tx3",
|
|
"tx4", "tx5", "tx6", "tx7",
|
|
"rx";
|
|
|
|
ethernet-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpsw_port1: port@1 {
|
|
reg = <1>;
|
|
ti,mac-only;
|
|
label = "port1";
|
|
ti,syscon-efuse = <&mcu_conf 0x200>;
|
|
phys = <&phy_gmii_sel 1>;
|
|
};
|
|
};
|
|
|
|
davinci_mdio: mdio@f00 {
|
|
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
|
|
reg = <0x0 0xf00 0x0 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&k3_clks 18 22>;
|
|
clock-names = "fck";
|
|
bus_freq = <1000000>;
|
|
};
|
|
|
|
cpts@3d000 {
|
|
compatible = "ti,am65-cpts";
|
|
reg = <0x0 0x3d000 0x0 0x400>;
|
|
clocks = <&k3_clks 18 2>;
|
|
clock-names = "cpts";
|
|
interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "cpts";
|
|
ti,cpts-ext-ts-inputs = <4>;
|
|
ti,cpts-periodic-outputs = <2>;
|
|
};
|
|
};
|
|
|
|
mcu_r5fss0: r5fss@41000000 {
|
|
compatible = "ti,j721e-r5fss";
|
|
ti,cluster-mode = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x41000000 0x00 0x41000000 0x20000>,
|
|
<0x41400000 0x00 0x41400000 0x20000>;
|
|
power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
mcu_r5fss0_core0: r5f@41000000 {
|
|
compatible = "ti,j721e-r5f";
|
|
reg = <0x41000000 0x00008000>,
|
|
<0x41010000 0x00008000>;
|
|
reg-names = "atcm", "btcm";
|
|
ti,sci = <&dmsc>;
|
|
ti,sci-dev-id = <250>;
|
|
ti,sci-proc-ids = <0x01 0xff>;
|
|
resets = <&k3_reset 250 1>;
|
|
firmware-name = "j7-mcu-r5f0_0-fw";
|
|
ti,atcm-enable = <1>;
|
|
ti,btcm-enable = <1>;
|
|
ti,loczrama = <1>;
|
|
};
|
|
|
|
mcu_r5fss0_core1: r5f@41400000 {
|
|
compatible = "ti,j721e-r5f";
|
|
reg = <0x41400000 0x00008000>,
|
|
<0x41410000 0x00008000>;
|
|
reg-names = "atcm", "btcm";
|
|
ti,sci = <&dmsc>;
|
|
ti,sci-dev-id = <251>;
|
|
ti,sci-proc-ids = <0x02 0xff>;
|
|
resets = <&k3_reset 251 1>;
|
|
firmware-name = "j7-mcu-r5f0_1-fw";
|
|
ti,atcm-enable = <1>;
|
|
ti,btcm-enable = <1>;
|
|
ti,loczrama = <1>;
|
|
};
|
|
};
|
|
|
|
mcu_mcan0: can@40528000 {
|
|
compatible = "bosch,m_can";
|
|
reg = <0x00 0x40528000 0x00 0x200>,
|
|
<0x00 0x40500000 0x00 0x8000>;
|
|
reg-names = "m_can", "message_ram";
|
|
power-domains = <&k3_pds 172 TI_SCI_PD_EXCLUSIVE>;
|
|
clocks = <&k3_clks 172 0>, <&k3_clks 172 1>;
|
|
clock-names = "hclk", "cclk";
|
|
interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "int0", "int1";
|
|
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mcu_mcan1: can@40568000 {
|
|
compatible = "bosch,m_can";
|
|
reg = <0x00 0x40568000 0x00 0x200>,
|
|
<0x00 0x40540000 0x00 0x8000>;
|
|
reg-names = "m_can", "message_ram";
|
|
power-domains = <&k3_pds 173 TI_SCI_PD_EXCLUSIVE>;
|
|
clocks = <&k3_clks 173 0>, <&k3_clks 173 1>;
|
|
clock-names = "hclk", "cclk";
|
|
interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "int0", "int1";
|
|
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mcu_spi0: spi@40300000 {
|
|
compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
|
|
reg = <0x00 0x040300000 0x00 0x400>;
|
|
interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>;
|
|
clocks = <&k3_clks 274 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mcu_spi1: spi@40310000 {
|
|
compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
|
|
reg = <0x00 0x040310000 0x00 0x400>;
|
|
interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>;
|
|
clocks = <&k3_clks 275 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mcu_spi2: spi@40320000 {
|
|
compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
|
|
reg = <0x00 0x040320000 0x00 0x400>;
|
|
interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
|
|
clocks = <&k3_clks 276 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
wkup_vtm0: temperature-sensor@42040000 {
|
|
compatible = "ti,j721e-vtm";
|
|
reg = <0x00 0x42040000 0x00 0x350>,
|
|
<0x00 0x42050000 0x00 0x350>,
|
|
<0x00 0x43000300 0x00 0x10>;
|
|
power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
|
|
#thermal-sensor-cells = <1>;
|
|
};
|
|
};
|