mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 17:07:38 +00:00
24a7a3c1c0
Synchronise device tree with linux v5.19-rc5. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
96 lines
1.8 KiB
Text
96 lines
1.8 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 NXP
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* Copyright (c) 2019 Engicam srl
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* Copyright (c) 2020 Amarula Solutions(India)
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*/
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/dts-v1/;
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#include "imx8mm.dtsi"
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#include "imx8mm-icore-mx8mm.dtsi"
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/ {
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model = "Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit";
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compatible = "engicam,icore-mx8mm-edimm2.2", "engicam,icore-mx8mm",
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"fsl,imx8mm";
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chosen {
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stdout-path = &uart2;
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};
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};
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&fec1 {
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status = "okay";
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};
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&i2c2 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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};
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&i2c4 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c4>;
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status = "okay";
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};
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&iomuxc {
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
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MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
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>;
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};
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pinctrl_i2c4: i2c4grp {
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fsl,pins = <
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MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
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MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
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MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
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>;
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};
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pinctrl_usdhc1_gpio: usdhc1gpiogrp {
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fsl,pins = <
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MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x41
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
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MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
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MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
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MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
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MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
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MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
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>;
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};
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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status = "okay";
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};
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/* SD */
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&usdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
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cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
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max-frequency = <50000000>;
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bus-width = <4>;
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no-1-8-v;
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keep-power-in-suspend;
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status = "okay";
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};
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