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https://github.com/AsahiLinux/u-boot
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de1d0a6995
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288 lines
8.6 KiB
C
288 lines
8.6 KiB
C
/*
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* Copyright 2004 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* mpc83xx.h
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*
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* MPC83xx specific definitions
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*/
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#ifndef __MPC83XX_H__
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#define __MPC83XX_H__
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#if defined(CONFIG_E300)
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#include <asm/e300.h>
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#endif
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/*
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* MPC83xx cpu provide RCR register to do reset thing specially. easier
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* to implement
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*/
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#define MPC83xx_RESET
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/*
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* System reset offset (PowerPC standard)
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*/
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#define EXC_OFF_SYS_RESET 0x0100
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/*
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* Default Internal Memory Register Space (Freescale recomandation)
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*/
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#define CONFIG_DEFAULT_IMMR 0xFF400000
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/*
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* Watchdog
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*/
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#define SWCRR 0x0204
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#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */
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#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */
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#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit. */
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#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */
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#define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
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#define SWCNR 0x0208
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#define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field.
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#define SWCNR_RES ~(SWCNR_SWCN)
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#define SWSRR 0x020E
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/*
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* Default Internal Memory Register Space (Freescale recomandation)
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*/
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#define IMMRBAR 0x0000
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#define IMMRBAR_BASE_ADDR 0xFFF00000 /* Identifies the 12 most-significant address bits of the base of the 1 MByte internal memory window. */
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#define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR)
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/*
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* Default Internal Memory Register Space (Freescale recomandation)
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*/
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#define LBLAWBAR0 0x0020
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#define LBLAWAR0 0x0024
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#define LBLAWBAR1 0x0028
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#define LBLAWAR1 0x002C
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#define LBLAWBAR2 0x0030
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#define LBLAWAR2 0x0034
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#define LBLAWBAR3 0x0038
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#define LBLAWAR3 0x003C
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/*
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* Base Registers & Option Registers
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*/
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#define BR0 0x5000
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#define BR1 0x5008
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#define BR2 0x5010
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#define BR3 0x5018
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#define BR4 0x5020
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#define BR5 0x5028
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#define BR6 0x5030
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#define BR7 0x5038
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#define BR_BA 0xFFFF8000
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#define BR_BA_SHIFT 15
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#define BR_PS 0x00001800
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#define BR_PS_SHIFT 11
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#define BR_DECC 0x00000600
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#define BR_DECC_SHIFT 9
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#define BR_WP 0x00000100
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#define BR_WP_SHIFT 8
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#define BR_MSEL 0x000000E0
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#define BR_MSEL_SHIFT 5
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#define BR_V 0x00000001
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#define BR_V_SHIFT 0
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#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
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#define OR0 0x5004
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#define OR1 0x500C
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#define OR2 0x5014
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#define OR3 0x501C
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#define OR4 0x5024
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#define OR5 0x502C
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#define OR6 0x5034
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#define OR7 0x503C
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#define OR_GPCM_AM 0xFFFF8000
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#define OR_GPCM_AM_SHIFT 15
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#define OR_GPCM_BCTLD 0x00001000
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#define OR_GPCM_BCTLD_SHIFT 12
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#define OR_GPCM_CSNT 0x00000800
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#define OR_GPCM_CSNT_SHIFT 11
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#define OR_GPCM_ACS 0x00000600
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#define OR_GPCM_ACS_SHIFT 9
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#define OR_GPCM_XACS 0x00000100
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#define OR_GPCM_XACS_SHIFT 8
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#define OR_GPCM_SCY 0x000000F0
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#define OR_GPCM_SCY_SHIFT 4
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#define OR_GPCM_SETA 0x00000008
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#define OR_GPCM_SETA_SHIFT 3
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#define OR_GPCM_TRLX 0x00000004
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#define OR_GPCM_TRLX_SHIFT 2
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#define OR_GPCM_EHTR 0x00000002
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#define OR_GPCM_EHTR_SHIFT 1
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#define OR_GPCM_EAD 0x00000001
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#define OR_GPCM_EAD_SHIFT 0
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#define OR_UPM_AM 0xFFFF8000
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#define OR_UPM_AM_SHIFT 15
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#define OR_UPM_XAM 0x00006000
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#define OR_UPM_XAM_SHIFT 13
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#define OR_UPM_BCTLD 0x00001000
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#define OR_UPM_BCTLD_SHIFT 12
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#define OR_UPM_BI 0x00000100
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#define OR_UPM_BI_SHIFT 8
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#define OR_UPM_TRLX 0x00000004
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#define OR_UPM_TRLX_SHIFT 2
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#define OR_UPM_EHTR 0x00000002
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#define OR_UPM_EHTR_SHIFT 1
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#define OR_UPM_EAD 0x00000001
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#define OR_UPM_EAD_SHIFT 0
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#define OR_SDRAM_AM 0xFFFF8000
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#define OR_SDRAM_AM_SHIFT 15
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#define OR_SDRAM_XAM 0x00006000
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#define OR_SDRAM_XAM_SHIFT 13
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#define OR_SDRAM_COLS 0x00001C00
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#define OR_SDRAM_COLS_SHIFT 10
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#define OR_SDRAM_ROWS 0x000001C0
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#define OR_SDRAM_ROWS_SHIFT 6
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#define OR_SDRAM_PMSEL 0x00000020
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#define OR_SDRAM_PMSEL_SHIFT 5
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#define OR_SDRAM_EAD 0x00000001
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#define OR_SDRAM_EAD_SHIFT 0
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/*
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* Hard Reset Configration Word - High
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*/
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#define HRCWH_PCI_AGENT 0x00000000
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#define HRCWH_PCI_HOST 0x80000000
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#define HRCWH_32_BIT_PCI 0x00000000
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#define HRCWH_64_BIT_PCI 0x40000000
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#define HRCWH_PCI1_ARBITER_DISABLE 0x00000000
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#define HRCWH_PCI1_ARBITER_ENABLE 0x20000000
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#define HRCWH_PCI2_ARBITER_DISABLE 0x00000000
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#define HRCWH_PCI2_ARBITER_ENABLE 0x10000000
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#define HRCWH_CORE_DISABLE 0x08000000
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#define HRCWH_CORE_ENABLE 0x00000000
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#define HRCWH_FROM_0X00000100 0x00000000
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#define HRCWH_FROM_0XFFF00100 0x04000000
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#define HRCWH_BOOTSEQ_DISABLE 0x00000000
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#define HRCWH_BOOTSEQ_NORMAL 0x01000000
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#define HRCWH_BOOTSEQ_EXTENDED 0x02000000
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#define HRCWH_SW_WATCHDOG_DISABLE 0x00000000
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#define HRCWH_SW_WATCHDOG_ENABLE 0x00800000
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#define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000
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#define HRCWH_ROM_LOC_PCI1 0x00100000
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#define HRCWH_ROM_LOC_PCI2 0x00200000
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#define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000
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#define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000
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#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
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#define HRCWH_TSEC1M_IN_RGMII 0x00000000
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#define HRCWH_TSEC1M_IN_RTBI 0x00004000
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#define HRCWH_TSEC1M_IN_GMII 0x00008000
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#define HRCWH_TSEC1M_IN_TBI 0x0000C000
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#define HRCWH_TSEC2M_IN_RGMII 0x00000000
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#define HRCWH_TSEC2M_IN_RTBI 0x00001000
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#define HRCWH_TSEC2M_IN_GMII 0x00002000
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#define HRCWH_TSEC2M_IN_TBI 0x00003000
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#define HRCWH_BIG_ENDIAN 0x00000000
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#define HRCWH_LITTLE_ENDIAN 0x00000008
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/*
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* Hard Reset Configration Word - Low
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*/
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#define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000
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#define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000
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#define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000
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#define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000
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#define HRCWL_CSB_TO_CLKIN_16X1 0x00000000
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#define HRCWL_CSB_TO_CLKIN_1X1 0x01000000
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#define HRCWL_CSB_TO_CLKIN_2X1 0x02000000
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#define HRCWL_CSB_TO_CLKIN_3X1 0x03000000
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#define HRCWL_CSB_TO_CLKIN_4X1 0x04000000
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#define HRCWL_CSB_TO_CLKIN_5X1 0x05000000
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#define HRCWL_CSB_TO_CLKIN_6X1 0x06000000
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#define HRCWL_CSB_TO_CLKIN_7X1 0x07000000
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#define HRCWL_CSB_TO_CLKIN_8X1 0x08000000
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#define HRCWL_CSB_TO_CLKIN_9X1 0x09000000
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#define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000
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#define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000
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#define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000
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#define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000
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#define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000
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#define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000
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#define HRCWL_VCO_BYPASS 0x00000000
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#define HRCWL_VCO_1X2 0x00000000
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#define HRCWL_VCO_1X4 0x00200000
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#define HRCWL_VCO_1X8 0x00400000
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#define HRCWL_CORE_TO_CSB_BYPASS 0x00000000
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#define HRCWL_CORE_TO_CSB_1X1 0x00020000
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#define HRCWL_CORE_TO_CSB_1_5X1 0x00030000
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#define HRCWL_CORE_TO_CSB_2X1 0x00040000
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#define HRCWL_CORE_TO_CSB_2_5X1 0x00050000
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#define HRCWL_CORE_TO_CSB_3X1 0x00060000
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/*
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* LCRR - Clock Ratio Register (10.3.1.16)
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*/
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#define LCRR_DBYP 0x80000000
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#define LCRR_DBYP_SHIFT 31
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#define LCRR_BUFCMDC 0x30000000
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#define LCRR_BUFCMDC_1 0x10000000
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#define LCRR_BUFCMDC_2 0x20000000
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#define LCRR_BUFCMDC_3 0x30000000
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#define LCRR_BUFCMDC_4 0x00000000
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#define LCRR_BUFCMDC_SHIFT 28
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#define LCRR_ECL 0x03000000
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#define LCRR_ECL_4 0x00000000
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#define LCRR_ECL_5 0x01000000
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#define LCRR_ECL_6 0x02000000
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#define LCRR_ECL_7 0x03000000
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#define LCRR_ECL_SHIFT 24
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#define LCRR_EADC 0x00030000
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#define LCRR_EADC_1 0x00010000
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#define LCRR_EADC_2 0x00020000
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#define LCRR_EADC_3 0x00030000
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#define LCRR_EADC_4 0x00000000
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#define LCRR_EADC_SHIFT 16
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#define LCRR_CLKDIV 0x0000000F
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#define LCRR_CLKDIV_2 0x00000002
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#define LCRR_CLKDIV_4 0x00000004
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#define LCRR_CLKDIV_8 0x00000008
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#define LCRR_CLKDIV_SHIFT 0
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#endif /* __MPC83XX_H__ */
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