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https://github.com/AsahiLinux/u-boot
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351 lines
10 KiB
C
351 lines
10 KiB
C
/******************************************************************************
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*
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* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
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* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
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* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
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* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
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* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
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* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
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* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
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* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
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* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
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* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
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* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
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* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE.
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*
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* (C) Copyright 2007-2008 Michal Simek
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* Michal SIMEK <monstr@monstr.eu>
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*
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* (c) Copyright 2003 Xilinx Inc.
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* All rights reserved.
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*
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******************************************************************************/
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#include <common.h>
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#include <net.h>
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#include <config.h>
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#include <asm/io.h>
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#undef DEBUG
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#define ENET_MAX_MTU PKTSIZE
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#define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
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#define ENET_ADDR_LENGTH 6
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/* EmacLite constants */
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#define XEL_BUFFER_OFFSET 0x0800 /* Next buffer's offset */
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#define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */
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#define XEL_TSR_OFFSET 0x07FC /* Tx status */
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#define XEL_RSR_OFFSET 0x17FC /* Rx status */
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#define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */
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/* Xmit complete */
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#define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL
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/* Xmit interrupt enable bit */
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#define XEL_TSR_XMIT_IE_MASK 0x00000008UL
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/* Buffer is active, SW bit only */
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#define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000UL
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/* Program the MAC address */
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#define XEL_TSR_PROGRAM_MASK 0x00000002UL
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/* define for programming the MAC address into the EMAC Lite */
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#define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
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/* Transmit packet length upper byte */
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#define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL
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/* Transmit packet length lower byte */
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#define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL
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/* Recv complete */
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#define XEL_RSR_RECV_DONE_MASK 0x00000001UL
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/* Recv interrupt enable bit */
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#define XEL_RSR_RECV_IE_MASK 0x00000008UL
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typedef struct {
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unsigned int baseaddress; /* Base address for device (IPIF) */
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unsigned int nexttxbuffertouse; /* Next TX buffer to write to */
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unsigned int nextrxbuffertouse; /* Next RX buffer to read from */
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unsigned char deviceid; /* Unique ID of device - for future */
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} xemaclite;
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static xemaclite emaclite;
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static char etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
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/* hardcoded MAC address for the Xilinx EMAC Core when env is nowhere*/
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#ifdef CONFIG_ENV_IS_NOWHERE
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static u8 emacaddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 };
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#else
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static u8 emacaddr[ENET_ADDR_LENGTH];
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#endif
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void xemaclite_alignedread (u32 * srcptr, void *destptr, unsigned bytecount)
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{
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unsigned int i;
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u32 alignbuffer;
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u32 *to32ptr;
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u32 *from32ptr;
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u8 *to8ptr;
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u8 *from8ptr;
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from32ptr = (u32 *) srcptr;
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/* Word aligned buffer, no correction needed. */
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to32ptr = (u32 *) destptr;
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while (bytecount > 3) {
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*to32ptr++ = *from32ptr++;
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bytecount -= 4;
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}
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to8ptr = (u8 *) to32ptr;
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alignbuffer = *from32ptr++;
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from8ptr = (u8 *) & alignbuffer;
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for (i = 0; i < bytecount; i++) {
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*to8ptr++ = *from8ptr++;
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}
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}
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void xemaclite_alignedwrite (void *srcptr, u32 destptr, unsigned bytecount)
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{
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unsigned i;
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u32 alignbuffer;
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u32 *to32ptr = (u32 *) destptr;
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u32 *from32ptr;
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u8 *to8ptr;
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u8 *from8ptr;
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from32ptr = (u32 *) srcptr;
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while (bytecount > 3) {
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*to32ptr++ = *from32ptr++;
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bytecount -= 4;
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}
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alignbuffer = 0;
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to8ptr = (u8 *) & alignbuffer;
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from8ptr = (u8 *) from32ptr;
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for (i = 0; i < bytecount; i++) {
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*to8ptr++ = *from8ptr++;
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}
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*to32ptr++ = alignbuffer;
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}
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void eth_halt (void)
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{
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debug ("eth_halt\n");
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}
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int eth_init (bd_t * bis)
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{
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debug ("EmacLite Initialization Started\n");
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memset (&emaclite, 0, sizeof (xemaclite));
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emaclite.baseaddress = XILINX_EMACLITE_BASEADDR;
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if (!getenv("ethaddr")) {
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memcpy(bis->bi_enetaddr, emacaddr, ENET_ADDR_LENGTH);
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}
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/*
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* TX - TX_PING & TX_PONG initialization
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*/
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/* Restart PING TX */
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out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, 0);
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/* Copy MAC address */
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xemaclite_alignedwrite (bis->bi_enetaddr,
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emaclite.baseaddress, ENET_ADDR_LENGTH);
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/* Set the length */
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out_be32 (emaclite.baseaddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
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/* Update the MAC address in the EMAC Lite */
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out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR);
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/* Wait for EMAC Lite to finish with the MAC address update */
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while ((in_be32 (emaclite.baseaddress + XEL_TSR_OFFSET) &
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XEL_TSR_PROG_MAC_ADDR) != 0) ;
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#ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
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/* The same operation with PONG TX */
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out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0);
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xemaclite_alignedwrite (bis->bi_enetaddr, emaclite.baseaddress +
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XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH);
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out_be32 (emaclite.baseaddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
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out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET,
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XEL_TSR_PROG_MAC_ADDR);
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while ((in_be32 (emaclite.baseaddress + XEL_TSR_OFFSET +
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XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0) ;
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#endif
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/*
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* RX - RX_PING & RX_PONG initialization
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*/
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/* Write out the value to flush the RX buffer */
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out_be32 (emaclite.baseaddress + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK);
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#ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
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out_be32 (emaclite.baseaddress + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET,
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XEL_RSR_RECV_IE_MASK);
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#endif
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debug ("EmacLite Initialization complete\n");
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return 0;
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}
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int xemaclite_txbufferavailable (xemaclite * instanceptr)
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{
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u32 reg;
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u32 txpingbusy;
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u32 txpongbusy;
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/*
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* Read the other buffer register
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* and determine if the other buffer is available
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*/
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reg = in_be32 (instanceptr->baseaddress +
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instanceptr->nexttxbuffertouse + 0);
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txpingbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
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XEL_TSR_XMIT_BUSY_MASK);
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reg = in_be32 (instanceptr->baseaddress +
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(instanceptr->nexttxbuffertouse ^ XEL_TSR_OFFSET) + 0);
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txpongbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
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XEL_TSR_XMIT_BUSY_MASK);
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return (!(txpingbusy && txpongbusy));
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}
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int eth_send (volatile void *ptr, int len) {
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unsigned int reg;
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unsigned int baseaddress;
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unsigned maxtry = 1000;
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if (len > ENET_MAX_MTU)
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len = ENET_MAX_MTU;
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while (!xemaclite_txbufferavailable (&emaclite) && maxtry) {
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udelay (10);
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maxtry--;
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}
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if (!maxtry) {
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printf ("Error: Timeout waiting for ethernet TX buffer\n");
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/* Restart PING TX */
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out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, 0);
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#ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
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out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET +
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XEL_BUFFER_OFFSET, 0);
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#endif
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return 0;
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}
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/* Determine the expected TX buffer address */
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baseaddress = (emaclite.baseaddress + emaclite.nexttxbuffertouse);
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/* Determine if the expected buffer address is empty */
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reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
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if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
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&& ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
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& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
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#ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
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emaclite.nexttxbuffertouse ^= XEL_BUFFER_OFFSET;
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#endif
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debug ("Send packet from 0x%x\n", baseaddress);
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/* Write the frame to the buffer */
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xemaclite_alignedwrite ((void *) ptr, baseaddress, len);
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out_be32 (baseaddress + XEL_TPLR_OFFSET,(len &
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(XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)));
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reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
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reg |= XEL_TSR_XMIT_BUSY_MASK;
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if ((reg & XEL_TSR_XMIT_IE_MASK) != 0) {
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reg |= XEL_TSR_XMIT_ACTIVE_MASK;
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}
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out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
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return 1;
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}
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#ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
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/* Switch to second buffer */
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baseaddress ^= XEL_BUFFER_OFFSET;
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/* Determine if the expected buffer address is empty */
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reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
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if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
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&& ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
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& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
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debug ("Send packet from 0x%x\n", baseaddress);
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/* Write the frame to the buffer */
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xemaclite_alignedwrite ((void *) ptr, baseaddress, len);
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out_be32 (baseaddress + XEL_TPLR_OFFSET,(len &
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(XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)));
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reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
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reg |= XEL_TSR_XMIT_BUSY_MASK;
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if ((reg & XEL_TSR_XMIT_IE_MASK) != 0) {
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reg |= XEL_TSR_XMIT_ACTIVE_MASK;
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}
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out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
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return 1;
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}
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#endif
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puts ("Error while sending frame\n");
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return 0;
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}
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int eth_rx (void)
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{
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unsigned int length;
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unsigned int reg;
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unsigned int baseaddress;
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baseaddress = emaclite.baseaddress + emaclite.nextrxbuffertouse;
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reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
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debug ("Testing data at address 0x%x\n", baseaddress);
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if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
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#ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
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emaclite.nextrxbuffertouse ^= XEL_BUFFER_OFFSET;
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#endif
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} else {
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#ifndef CONFIG_XILINX_EMACLITE_RX_PING_PONG
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debug ("No data was available - address 0x%x\n", baseaddress);
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return 0;
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#else
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baseaddress ^= XEL_BUFFER_OFFSET;
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reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
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if ((reg & XEL_RSR_RECV_DONE_MASK) !=
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XEL_RSR_RECV_DONE_MASK) {
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debug ("No data was available - address 0x%x\n",
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baseaddress);
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return 0;
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}
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#endif
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}
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/* Get the length of the frame that arrived */
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switch(((in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC)) &
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0xFFFF0000 ) >> 16) {
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case 0x806:
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length = 42 + 20; /* FIXME size of ARP */
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debug ("ARP Packet\n");
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break;
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case 0x800:
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length = 14 + 14 +
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(((in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0x10)) &
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0xFFFF0000) >> 16); /* FIXME size of IP packet */
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debug ("IP Packet\n");
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break;
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default:
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debug ("Other Packet\n");
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length = ENET_MAX_MTU;
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break;
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}
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xemaclite_alignedread ((u32 *) (baseaddress + XEL_RXBUFF_OFFSET),
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etherrxbuff, length);
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/* Acknowledge the frame */
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reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
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reg &= ~XEL_RSR_RECV_DONE_MASK;
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out_be32 (baseaddress + XEL_RSR_OFFSET, reg);
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debug ("Packet receive from 0x%x, length %dB\n", baseaddress, length);
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NetReceive ((uchar *) etherrxbuff, length);
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return 1;
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}
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