mirror of
https://github.com/AsahiLinux/u-boot
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b12dc5d6fa
This driver supports Rockchip NFC (NAND Flash Controller) found on RK3308, RK2928, RKPX30, RV1108 and other SOCs. The driver has been tested using 8-bit NAND interface on the ARM based RK3308 platform. Support Rockchip SoCs and NFC versions: - PX30 and RK3326(NFCv900). ECC: 16/40/60/70 bits/1KB. CLOCK: ahb and nfc. - RK3308 and RV1108(NFCv800). ECC: 16 bits/1KB. CLOCK: ahb and nfc. - RK3036 and RK3128(NFCv622). ECC: 16/24/40/60 bits/1KB. CLOCK: ahb and nfc. - RK3066, RK3188 and RK2928(NFCv600). ECC: 16/24/40/60 bits/1KB. CLOCK: ahb. Supported features: - Read full page data by DMA. - Support HW ECC(one step is 1KB). - Support 2 - 32K page size. - Support 8 CS(depend on SoCs) Limitations: - No support for the ecc step size is 512. - Untested on some SoCs. - No support for subpages. - No support for the builtin randomizer. - The original bad block mask is not supported. It is recommended to use the BBT(bad block table). Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
1253 lines
31 KiB
C
1253 lines
31 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Rockchip NAND Flash controller driver.
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* Copyright (C) 2021 Rockchip Inc.
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* Author: Yifeng Zhao <yifeng.zhao@rock-chips.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <clk.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <dm/devres.h>
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#include <fdtdec.h>
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#include <inttypes.h>
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#include <linux/delay.h>
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#include <linux/dma-direction.h>
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#include <linux/dma-mapping.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <memalign.h>
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#include <nand.h>
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/*
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* NFC Page Data Layout:
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* 1024 bytes data + 4Bytes sys data + 28Bytes~124Bytes ECC data +
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* 1024 bytes data + 4Bytes sys data + 28Bytes~124Bytes ECC data +
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* ......
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* NAND Page Data Layout:
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* 1024 * n data + m Bytes oob
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* Original Bad Block Mask Location:
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* First byte of oob(spare).
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* nand_chip->oob_poi data layout:
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* 4Bytes sys data + .... + 4Bytes sys data + ECC data.
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*/
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/* NAND controller register definition */
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#define NFC_READ (0)
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#define NFC_WRITE (1)
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#define NFC_FMCTL (0x00)
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#define FMCTL_CE_SEL_M 0xFF
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#define FMCTL_CE_SEL(x) (1 << (x))
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#define FMCTL_WP BIT(8)
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#define FMCTL_RDY BIT(9)
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#define NFC_FMWAIT (0x04)
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#define FLCTL_RST BIT(0)
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#define FLCTL_WR (1) /* 0: read, 1: write */
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#define FLCTL_XFER_ST BIT(2)
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#define FLCTL_XFER_EN BIT(3)
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#define FLCTL_ACORRECT BIT(10) /* Auto correct error bits. */
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#define FLCTL_XFER_READY BIT(20)
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#define FLCTL_XFER_SECTOR (22)
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#define FLCTL_TOG_FIX BIT(29)
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#define BCHCTL_BANK_M (7 << 5)
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#define BCHCTL_BANK (5)
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#define DMA_ST BIT(0)
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#define DMA_WR (1) /* 0: write, 1: read */
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#define DMA_EN BIT(2)
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#define DMA_AHB_SIZE (3) /* 0: 1, 1: 2, 2: 4 */
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#define DMA_BURST_SIZE (6) /* 0: 1, 3: 4, 5: 8, 7: 16 */
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#define DMA_INC_NUM (9) /* 1 - 16 */
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#define ECC_ERR_CNT(x, e) ((((x) >> (e).low) & (e).low_mask) |\
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(((x) >> (e).high) & (e).high_mask) << (e).low_bn)
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#define INT_DMA BIT(0)
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#define NFC_BANK (0x800)
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#define NFC_BANK_STEP (0x100)
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#define BANK_DATA (0x00)
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#define BANK_ADDR (0x04)
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#define BANK_CMD (0x08)
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#define NFC_SRAM0 (0x1000)
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#define NFC_SRAM1 (0x1400)
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#define NFC_SRAM_SIZE (0x400)
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#define NFC_TIMEOUT_MS (500)
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#define NFC_MAX_OOB_PER_STEP 128
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#define NFC_MIN_OOB_PER_STEP 64
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#define MAX_DATA_SIZE 0xFFFC
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#define MAX_ADDRESS_CYC 6
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#define NFC_ECC_MAX_MODES 4
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#define NFC_RB_DELAY_US 50
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#define NFC_MAX_PAGE_SIZE (16 * 1024)
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#define NFC_MAX_OOB_SIZE (16 * 128)
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#define NFC_MAX_NSELS (8) /* Some Socs only have 1 or 2 CSs. */
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#define NFC_SYS_DATA_SIZE (4) /* 4 bytes sys data in oob pre 1024 data.*/
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#define RK_DEFAULT_CLOCK_RATE (150 * 1000 * 1000) /* 150 Mhz */
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#define ACCTIMING(csrw, rwpw, rwcs) ((csrw) << 12 | (rwpw) << 5 | (rwcs))
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enum nfc_type {
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NFC_V6,
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NFC_V8,
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NFC_V9,
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};
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/**
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* struct rk_ecc_cnt_status: represent a ecc status data.
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* @err_flag_bit: error flag bit index at register.
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* @low: ECC count low bit index at register.
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* @low_mask: mask bit.
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* @low_bn: ECC count low bit number.
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* @high: ECC count high bit index at register.
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* @high_mask: mask bit
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*/
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struct ecc_cnt_status {
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u8 err_flag_bit;
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u8 low;
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u8 low_mask;
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u8 low_bn;
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u8 high;
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u8 high_mask;
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};
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/**
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* @type: NFC version
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* @ecc_strengths: ECC strengths
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* @ecc_cfgs: ECC config values
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* @flctl_off: FLCTL register offset
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* @bchctl_off: BCHCTL register offset
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* @dma_data_buf_off: DMA_DATA_BUF register offset
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* @dma_oob_buf_off: DMA_OOB_BUF register offset
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* @dma_cfg_off: DMA_CFG register offset
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* @dma_st_off: DMA_ST register offset
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* @bch_st_off: BCG_ST register offset
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* @randmz_off: RANDMZ register offset
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* @int_en_off: interrupt enable register offset
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* @int_clr_off: interrupt clean register offset
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* @int_st_off: interrupt status register offset
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* @oob0_off: oob0 register offset
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* @oob1_off: oob1 register offset
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* @ecc0: represent ECC0 status data
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* @ecc1: represent ECC1 status data
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*/
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struct nfc_cfg {
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enum nfc_type type;
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u8 ecc_strengths[NFC_ECC_MAX_MODES];
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u32 ecc_cfgs[NFC_ECC_MAX_MODES];
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u32 flctl_off;
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u32 bchctl_off;
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u32 dma_cfg_off;
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u32 dma_data_buf_off;
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u32 dma_oob_buf_off;
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u32 dma_st_off;
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u32 bch_st_off;
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u32 randmz_off;
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u32 int_en_off;
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u32 int_clr_off;
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u32 int_st_off;
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u32 oob0_off;
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u32 oob1_off;
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struct ecc_cnt_status ecc0;
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struct ecc_cnt_status ecc1;
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};
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struct rk_nfc_nand_chip {
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struct nand_chip chip;
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u16 boot_blks;
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u16 metadata_size;
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u32 boot_ecc;
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u32 timing;
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u8 nsels;
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u8 sels[0];
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/* Nothing after this field. */
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};
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struct rk_nfc {
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struct nand_hw_control controller;
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const struct nfc_cfg *cfg;
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struct udevice *dev;
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struct clk *nfc_clk;
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struct clk *ahb_clk;
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void __iomem *regs;
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int selected_bank;
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u32 band_offset;
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u32 cur_ecc;
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u32 cur_timing;
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u8 *page_buf;
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u32 *oob_buf;
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unsigned long assigned_cs;
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};
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static inline struct rk_nfc_nand_chip *rk_nfc_to_rknand(struct nand_chip *chip)
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{
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return container_of(chip, struct rk_nfc_nand_chip, chip);
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}
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static inline u8 *rk_nfc_buf_to_data_ptr(struct nand_chip *chip, const u8 *p, int i)
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{
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return (u8 *)p + i * chip->ecc.size;
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}
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static inline u8 *rk_nfc_buf_to_oob_ptr(struct nand_chip *chip, int i)
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{
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u8 *poi;
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poi = chip->oob_poi + i * NFC_SYS_DATA_SIZE;
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return poi;
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}
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static inline u8 *rk_nfc_buf_to_oob_ecc_ptr(struct nand_chip *chip, int i)
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{
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struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
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u8 *poi;
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poi = chip->oob_poi + rknand->metadata_size + chip->ecc.bytes * i;
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return poi;
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}
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static inline int rk_nfc_data_len(struct nand_chip *chip)
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{
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return chip->ecc.size + chip->ecc.bytes + NFC_SYS_DATA_SIZE;
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}
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static inline u8 *rk_nfc_data_ptr(struct nand_chip *chip, int i)
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{
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struct rk_nfc *nfc = nand_get_controller_data(chip);
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return nfc->page_buf + i * rk_nfc_data_len(chip);
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}
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static inline u8 *rk_nfc_oob_ptr(struct nand_chip *chip, int i)
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{
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struct rk_nfc *nfc = nand_get_controller_data(chip);
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return nfc->page_buf + i * rk_nfc_data_len(chip) + chip->ecc.size;
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}
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static int rk_nfc_hw_ecc_setup(struct nand_chip *chip, u32 strength)
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{
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struct rk_nfc *nfc = nand_get_controller_data(chip);
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u32 reg, i;
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for (i = 0; i < NFC_ECC_MAX_MODES; i++) {
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if (strength == nfc->cfg->ecc_strengths[i]) {
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reg = nfc->cfg->ecc_cfgs[i];
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break;
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}
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}
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if (i >= NFC_ECC_MAX_MODES)
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return -EINVAL;
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writel(reg, nfc->regs + nfc->cfg->bchctl_off);
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/* Save chip ECC setting */
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nfc->cur_ecc = strength;
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return 0;
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}
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static void rk_nfc_select_chip(struct mtd_info *mtd, int cs)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct rk_nfc *nfc = nand_get_controller_data(chip);
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struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
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struct nand_ecc_ctrl *ecc = &chip->ecc;
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u32 val;
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if (cs < 0) {
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nfc->selected_bank = -1;
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/* Deselect the currently selected target. */
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val = readl(nfc->regs + NFC_FMCTL);
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val &= ~FMCTL_CE_SEL_M;
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writel(val, nfc->regs + NFC_FMCTL);
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return;
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}
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nfc->selected_bank = rknand->sels[cs];
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nfc->band_offset = NFC_BANK + nfc->selected_bank * NFC_BANK_STEP;
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val = readl(nfc->regs + NFC_FMCTL);
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val &= ~FMCTL_CE_SEL_M;
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val |= FMCTL_CE_SEL(nfc->selected_bank);
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writel(val, nfc->regs + NFC_FMCTL);
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/*
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* Compare current chip timing with selected chip timing and
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* change if needed.
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*/
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if (nfc->cur_timing != rknand->timing) {
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writel(rknand->timing, nfc->regs + NFC_FMWAIT);
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nfc->cur_timing = rknand->timing;
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}
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/*
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* Compare current chip ECC setting with selected chip ECC setting and
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* change if needed.
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*/
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if (nfc->cur_ecc != ecc->strength)
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rk_nfc_hw_ecc_setup(chip, ecc->strength);
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}
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static inline int rk_nfc_wait_ioready(struct rk_nfc *nfc)
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{
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u32 timeout = (CONFIG_SYS_HZ * NFC_TIMEOUT_MS) / 1000;
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u32 time_start;
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time_start = get_timer(0);
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do {
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if (readl(nfc->regs + NFC_FMCTL) & FMCTL_RDY)
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return 0;
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} while (get_timer(time_start) < timeout);
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dev_err(nfc->dev, "wait for io ready timedout\n");
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return -ETIMEDOUT;
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}
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static void rk_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct rk_nfc *nfc = nand_get_controller_data(chip);
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void __iomem *bank_base;
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int i = 0;
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bank_base = nfc->regs + nfc->band_offset + BANK_DATA;
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for (i = 0; i < len; i++)
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buf[i] = readl(bank_base);
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}
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static void rk_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct rk_nfc *nfc = nand_get_controller_data(chip);
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void __iomem *bank_base;
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int i = 0;
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bank_base = nfc->regs + nfc->band_offset + BANK_DATA;
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for (i = 0; i < len; i++)
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writel(buf[i], bank_base);
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}
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static void rk_nfc_cmd(struct mtd_info *mtd, int dat, unsigned int ctrl)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct rk_nfc *nfc = nand_get_controller_data(chip);
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void __iomem *bank_base;
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bank_base = nfc->regs + nfc->band_offset;
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if (ctrl & NAND_CTRL_CHANGE) {
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if (ctrl & NAND_ALE)
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bank_base += BANK_ADDR;
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else if (ctrl & NAND_CLE)
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bank_base += BANK_CMD;
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chip->IO_ADDR_W = bank_base;
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}
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if (dat != NAND_CMD_NONE)
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writel(dat & 0xFF, chip->IO_ADDR_W);
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}
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static uint8_t rockchip_nand_read_byte(struct mtd_info *mtd)
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{
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uint8_t ret;
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rk_nfc_read_buf(mtd, &ret, 1);
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return ret;
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}
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static int rockchip_nand_dev_ready(struct mtd_info *mtd)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct rk_nfc *nfc = nand_get_controller_data(chip);
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if (readl(nfc->regs + NFC_FMCTL) & FMCTL_RDY)
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return 1;
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return 0;
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}
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static void rk_nfc_xfer_start(struct rk_nfc *nfc, u8 rw, u8 n_KB,
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dma_addr_t dma_data, dma_addr_t dma_oob)
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{
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u32 dma_reg, fl_reg, bch_reg;
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dma_reg = DMA_ST | ((!rw) << DMA_WR) | DMA_EN | (2 << DMA_AHB_SIZE) |
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(7 << DMA_BURST_SIZE) | (16 << DMA_INC_NUM);
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fl_reg = (rw << FLCTL_WR) | FLCTL_XFER_EN | FLCTL_ACORRECT |
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(n_KB << FLCTL_XFER_SECTOR) | FLCTL_TOG_FIX;
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if (nfc->cfg->type == NFC_V6 || nfc->cfg->type == NFC_V8) {
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bch_reg = readl_relaxed(nfc->regs + nfc->cfg->bchctl_off);
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bch_reg = (bch_reg & (~BCHCTL_BANK_M)) |
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(nfc->selected_bank << BCHCTL_BANK);
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writel(bch_reg, nfc->regs + nfc->cfg->bchctl_off);
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}
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writel(dma_reg, nfc->regs + nfc->cfg->dma_cfg_off);
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writel((u32)dma_data, nfc->regs + nfc->cfg->dma_data_buf_off);
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writel((u32)dma_oob, nfc->regs + nfc->cfg->dma_oob_buf_off);
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writel(fl_reg, nfc->regs + nfc->cfg->flctl_off);
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fl_reg |= FLCTL_XFER_ST;
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writel(fl_reg, nfc->regs + nfc->cfg->flctl_off);
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}
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static int rk_nfc_wait_for_xfer_done(struct rk_nfc *nfc)
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{
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unsigned long timeout = (CONFIG_SYS_HZ * NFC_TIMEOUT_MS) / 1000;
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void __iomem *ptr = nfc->regs + nfc->cfg->flctl_off;
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u32 time_start;
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time_start = get_timer(0);
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do {
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if (readl(ptr) & FLCTL_XFER_READY)
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return 0;
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} while (get_timer(time_start) < timeout);
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dev_err(nfc->dev, "wait for io ready timedout\n");
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return -ETIMEDOUT;
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}
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static int rk_nfc_write_page_raw(struct mtd_info *mtd,
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struct nand_chip *chip,
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const u8 *buf,
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int oob_required,
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int page)
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{
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struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
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struct rk_nfc *nfc = nand_get_controller_data(chip);
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struct nand_ecc_ctrl *ecc = &chip->ecc;
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int i, pages_per_blk;
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pages_per_blk = mtd->erasesize / mtd->writesize;
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if ((page < (pages_per_blk * rknand->boot_blks)) &&
|
|
rknand->boot_ecc != ecc->strength) {
|
|
/*
|
|
* There's currently no method to notify the MTD framework that
|
|
* a different ECC strength is in use for the boot blocks.
|
|
*/
|
|
return -EIO;
|
|
}
|
|
|
|
if (!buf)
|
|
memset(nfc->page_buf, 0xff, mtd->writesize + mtd->oobsize);
|
|
|
|
for (i = 0; i < ecc->steps; i++) {
|
|
/* Copy data to the NFC buffer. */
|
|
if (buf)
|
|
memcpy(rk_nfc_data_ptr(chip, i),
|
|
rk_nfc_buf_to_data_ptr(chip, buf, i),
|
|
ecc->size);
|
|
/*
|
|
* The first four bytes of OOB are reserved for the
|
|
* boot ROM. In some debugging cases, such as with a
|
|
* read, erase and write back test these 4 bytes stored
|
|
* in OOB also need to be written back.
|
|
*
|
|
* The function nand_block_bad detects bad blocks like:
|
|
*
|
|
* bad = chip->oob_poi[chip->badblockpos];
|
|
*
|
|
* chip->badblockpos == 0 for a large page NAND Flash,
|
|
* so chip->oob_poi[0] is the bad block mask (BBM).
|
|
*
|
|
* The OOB data layout on the NFC is:
|
|
*
|
|
* PA0 PA1 PA2 PA3 | BBM OOB1 OOB2 OOB3 | ...
|
|
*
|
|
* or
|
|
*
|
|
* 0xFF 0xFF 0xFF 0xFF | BBM OOB1 OOB2 OOB3 | ...
|
|
*
|
|
* The code here just swaps the first 4 bytes with the last
|
|
* 4 bytes without losing any data.
|
|
*
|
|
* The chip->oob_poi data layout:
|
|
*
|
|
* BBM OOB1 OOB2 OOB3 |......| PA0 PA1 PA2 PA3
|
|
*
|
|
* The rk_nfc_ooblayout_free() function already has reserved
|
|
* these 4 bytes with:
|
|
*
|
|
* oob_region->offset = NFC_SYS_DATA_SIZE + 2;
|
|
*/
|
|
if (!i)
|
|
memcpy(rk_nfc_oob_ptr(chip, i),
|
|
rk_nfc_buf_to_oob_ptr(chip, ecc->steps - 1),
|
|
NFC_SYS_DATA_SIZE);
|
|
else
|
|
memcpy(rk_nfc_oob_ptr(chip, i),
|
|
rk_nfc_buf_to_oob_ptr(chip, i - 1),
|
|
NFC_SYS_DATA_SIZE);
|
|
/* Copy ECC data to the NFC buffer. */
|
|
memcpy(rk_nfc_oob_ptr(chip, i) + NFC_SYS_DATA_SIZE,
|
|
rk_nfc_buf_to_oob_ecc_ptr(chip, i),
|
|
ecc->bytes);
|
|
}
|
|
|
|
nand_prog_page_begin_op(chip, page, 0, NULL, 0);
|
|
rk_nfc_write_buf(mtd, buf, mtd->writesize + mtd->oobsize);
|
|
return nand_prog_page_end_op(chip);
|
|
}
|
|
|
|
static int rk_nfc_write_page_hwecc(struct mtd_info *mtd,
|
|
struct nand_chip *chip,
|
|
const u8 *buf,
|
|
int oob_required,
|
|
int page)
|
|
{
|
|
struct rk_nfc *nfc = nand_get_controller_data(chip);
|
|
struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
|
|
struct nand_ecc_ctrl *ecc = &chip->ecc;
|
|
int oob_step = (ecc->bytes > 60) ? NFC_MAX_OOB_PER_STEP :
|
|
NFC_MIN_OOB_PER_STEP;
|
|
int pages_per_blk = mtd->erasesize / mtd->writesize;
|
|
int ret = 0, i, boot_rom_mode = 0;
|
|
dma_addr_t dma_data, dma_oob;
|
|
u32 reg;
|
|
u8 *oob;
|
|
|
|
nand_prog_page_begin_op(chip, page, 0, NULL, 0);
|
|
|
|
if (buf)
|
|
memcpy(nfc->page_buf, buf, mtd->writesize);
|
|
else
|
|
memset(nfc->page_buf, 0xFF, mtd->writesize);
|
|
|
|
/*
|
|
* The first blocks (4, 8 or 16 depending on the device) are used
|
|
* by the boot ROM and the first 32 bits of OOB need to link to
|
|
* the next page address in the same block. We can't directly copy
|
|
* OOB data from the MTD framework, because this page address
|
|
* conflicts for example with the bad block marker (BBM),
|
|
* so we shift all OOB data including the BBM with 4 byte positions.
|
|
* As a consequence the OOB size available to the MTD framework is
|
|
* also reduced with 4 bytes.
|
|
*
|
|
* PA0 PA1 PA2 PA3 | BBM OOB1 OOB2 OOB3 | ...
|
|
*
|
|
* If a NAND is not a boot medium or the page is not a boot block,
|
|
* the first 4 bytes are left untouched by writing 0xFF to them.
|
|
*
|
|
* 0xFF 0xFF 0xFF 0xFF | BBM OOB1 OOB2 OOB3 | ...
|
|
*
|
|
* Configure the ECC algorithm supported by the boot ROM.
|
|
*/
|
|
if (page < (pages_per_blk * rknand->boot_blks)) {
|
|
boot_rom_mode = 1;
|
|
if (rknand->boot_ecc != ecc->strength)
|
|
rk_nfc_hw_ecc_setup(chip, rknand->boot_ecc);
|
|
}
|
|
|
|
for (i = 0; i < ecc->steps; i++) {
|
|
if (!i) {
|
|
reg = 0xFFFFFFFF;
|
|
} else {
|
|
oob = chip->oob_poi + (i - 1) * NFC_SYS_DATA_SIZE;
|
|
reg = oob[0] | oob[1] << 8 | oob[2] << 16 |
|
|
oob[3] << 24;
|
|
}
|
|
|
|
if (!i && boot_rom_mode)
|
|
reg = (page & (pages_per_blk - 1)) * 4;
|
|
|
|
if (nfc->cfg->type == NFC_V9)
|
|
nfc->oob_buf[i] = reg;
|
|
else
|
|
nfc->oob_buf[i * (oob_step / 4)] = reg;
|
|
}
|
|
|
|
dma_data = dma_map_single((void *)nfc->page_buf,
|
|
mtd->writesize, DMA_TO_DEVICE);
|
|
dma_oob = dma_map_single(nfc->oob_buf,
|
|
ecc->steps * oob_step,
|
|
DMA_TO_DEVICE);
|
|
|
|
rk_nfc_xfer_start(nfc, NFC_WRITE, ecc->steps, dma_data,
|
|
dma_oob);
|
|
ret = rk_nfc_wait_for_xfer_done(nfc);
|
|
|
|
dma_unmap_single(dma_data, mtd->writesize,
|
|
DMA_TO_DEVICE);
|
|
dma_unmap_single(dma_oob, ecc->steps * oob_step,
|
|
DMA_TO_DEVICE);
|
|
|
|
if (boot_rom_mode && rknand->boot_ecc != ecc->strength)
|
|
rk_nfc_hw_ecc_setup(chip, ecc->strength);
|
|
|
|
if (ret) {
|
|
dev_err(nfc->dev, "write: wait transfer done timeout.\n");
|
|
return -ETIMEDOUT;
|
|
}
|
|
|
|
return nand_prog_page_end_op(chip);
|
|
}
|
|
|
|
static int rk_nfc_write_oob(struct mtd_info *mtd,
|
|
struct nand_chip *chip, int page)
|
|
{
|
|
return rk_nfc_write_page_hwecc(mtd, chip, NULL, 1, page);
|
|
}
|
|
|
|
static int rk_nfc_read_page_raw(struct mtd_info *mtd,
|
|
struct nand_chip *chip,
|
|
u8 *buf,
|
|
int oob_required,
|
|
int page)
|
|
{
|
|
struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
|
|
struct rk_nfc *nfc = nand_get_controller_data(chip);
|
|
struct nand_ecc_ctrl *ecc = &chip->ecc;
|
|
int i, pages_per_blk;
|
|
|
|
pages_per_blk = mtd->erasesize / mtd->writesize;
|
|
if ((page < (pages_per_blk * rknand->boot_blks)) &&
|
|
nfc->selected_bank == 0 &&
|
|
rknand->boot_ecc != ecc->strength) {
|
|
/*
|
|
* There's currently no method to notify the MTD framework that
|
|
* a different ECC strength is in use for the boot blocks.
|
|
*/
|
|
return -EIO;
|
|
}
|
|
|
|
nand_read_page_op(chip, page, 0, NULL, 0);
|
|
rk_nfc_read_buf(mtd, nfc->page_buf, mtd->writesize + mtd->oobsize);
|
|
for (i = 0; i < ecc->steps; i++) {
|
|
/*
|
|
* The first four bytes of OOB are reserved for the
|
|
* boot ROM. In some debugging cases, such as with a read,
|
|
* erase and write back test, these 4 bytes also must be
|
|
* saved somewhere, otherwise this information will be
|
|
* lost during a write back.
|
|
*/
|
|
if (!i)
|
|
memcpy(rk_nfc_buf_to_oob_ptr(chip, ecc->steps - 1),
|
|
rk_nfc_oob_ptr(chip, i),
|
|
NFC_SYS_DATA_SIZE);
|
|
else
|
|
memcpy(rk_nfc_buf_to_oob_ptr(chip, i - 1),
|
|
rk_nfc_oob_ptr(chip, i),
|
|
NFC_SYS_DATA_SIZE);
|
|
|
|
/* Copy ECC data from the NFC buffer. */
|
|
memcpy(rk_nfc_buf_to_oob_ecc_ptr(chip, i),
|
|
rk_nfc_oob_ptr(chip, i) + NFC_SYS_DATA_SIZE,
|
|
ecc->bytes);
|
|
|
|
/* Copy data from the NFC buffer. */
|
|
if (buf)
|
|
memcpy(rk_nfc_buf_to_data_ptr(chip, buf, i),
|
|
rk_nfc_data_ptr(chip, i),
|
|
ecc->size);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rk_nfc_read_page_hwecc(struct mtd_info *mtd,
|
|
struct nand_chip *chip,
|
|
u8 *buf,
|
|
int oob_required,
|
|
int page)
|
|
{
|
|
struct rk_nfc *nfc = nand_get_controller_data(chip);
|
|
struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
|
|
struct nand_ecc_ctrl *ecc = &chip->ecc;
|
|
int oob_step = (ecc->bytes > 60) ? NFC_MAX_OOB_PER_STEP :
|
|
NFC_MIN_OOB_PER_STEP;
|
|
int pages_per_blk = mtd->erasesize / mtd->writesize;
|
|
dma_addr_t dma_data, dma_oob;
|
|
int ret = 0, i, cnt, boot_rom_mode = 0;
|
|
int max_bitflips = 0, bch_st, ecc_fail = 0;
|
|
u8 *oob;
|
|
u32 tmp;
|
|
|
|
nand_read_page_op(chip, page, 0, NULL, 0);
|
|
|
|
dma_data = dma_map_single(nfc->page_buf,
|
|
mtd->writesize,
|
|
DMA_FROM_DEVICE);
|
|
dma_oob = dma_map_single(nfc->oob_buf,
|
|
ecc->steps * oob_step,
|
|
DMA_FROM_DEVICE);
|
|
|
|
/*
|
|
* The first blocks (4, 8 or 16 depending on the device)
|
|
* are used by the boot ROM.
|
|
* Configure the ECC algorithm supported by the boot ROM.
|
|
*/
|
|
if (page < (pages_per_blk * rknand->boot_blks) &&
|
|
nfc->selected_bank == 0) {
|
|
boot_rom_mode = 1;
|
|
if (rknand->boot_ecc != ecc->strength)
|
|
rk_nfc_hw_ecc_setup(chip, rknand->boot_ecc);
|
|
}
|
|
|
|
rk_nfc_xfer_start(nfc, NFC_READ, ecc->steps, dma_data,
|
|
dma_oob);
|
|
ret = rk_nfc_wait_for_xfer_done(nfc);
|
|
|
|
dma_unmap_single(dma_data, mtd->writesize,
|
|
DMA_FROM_DEVICE);
|
|
dma_unmap_single(dma_oob, ecc->steps * oob_step,
|
|
DMA_FROM_DEVICE);
|
|
|
|
if (ret) {
|
|
ret = -ETIMEDOUT;
|
|
dev_err(nfc->dev, "read: wait transfer done timeout.\n");
|
|
goto timeout_err;
|
|
}
|
|
|
|
for (i = 1; i < ecc->steps; i++) {
|
|
oob = chip->oob_poi + (i - 1) * NFC_SYS_DATA_SIZE;
|
|
if (nfc->cfg->type == NFC_V9)
|
|
tmp = nfc->oob_buf[i];
|
|
else
|
|
tmp = nfc->oob_buf[i * (oob_step / 4)];
|
|
*oob++ = (u8)tmp;
|
|
*oob++ = (u8)(tmp >> 8);
|
|
*oob++ = (u8)(tmp >> 16);
|
|
*oob++ = (u8)(tmp >> 24);
|
|
}
|
|
|
|
for (i = 0; i < (ecc->steps / 2); i++) {
|
|
bch_st = readl_relaxed(nfc->regs +
|
|
nfc->cfg->bch_st_off + i * 4);
|
|
if (bch_st & BIT(nfc->cfg->ecc0.err_flag_bit) ||
|
|
bch_st & BIT(nfc->cfg->ecc1.err_flag_bit)) {
|
|
mtd->ecc_stats.failed++;
|
|
ecc_fail = 1;
|
|
} else {
|
|
cnt = ECC_ERR_CNT(bch_st, nfc->cfg->ecc0);
|
|
mtd->ecc_stats.corrected += cnt;
|
|
max_bitflips = max_t(u32, max_bitflips, cnt);
|
|
|
|
cnt = ECC_ERR_CNT(bch_st, nfc->cfg->ecc1);
|
|
mtd->ecc_stats.corrected += cnt;
|
|
max_bitflips = max_t(u32, max_bitflips, cnt);
|
|
}
|
|
}
|
|
|
|
if (buf)
|
|
memcpy(buf, nfc->page_buf, mtd->writesize);
|
|
|
|
timeout_err:
|
|
if (boot_rom_mode && rknand->boot_ecc != ecc->strength)
|
|
rk_nfc_hw_ecc_setup(chip, ecc->strength);
|
|
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (ecc_fail) {
|
|
dev_err(nfc->dev, "read page: %x ecc error!\n", page);
|
|
return 0;
|
|
}
|
|
|
|
return max_bitflips;
|
|
}
|
|
|
|
static int rk_nfc_read_oob(struct mtd_info *mtd,
|
|
struct nand_chip *chip, int page)
|
|
{
|
|
return rk_nfc_read_page_hwecc(mtd, chip, NULL, 1, page);
|
|
}
|
|
|
|
static inline void rk_nfc_hw_init(struct rk_nfc *nfc)
|
|
{
|
|
/* Disable flash wp. */
|
|
writel(FMCTL_WP, nfc->regs + NFC_FMCTL);
|
|
/* Config default timing 40ns at 150 Mhz NFC clock. */
|
|
writel(0x1081, nfc->regs + NFC_FMWAIT);
|
|
nfc->cur_timing = 0x1081;
|
|
/* Disable randomizer and DMA. */
|
|
writel(0, nfc->regs + nfc->cfg->randmz_off);
|
|
writel(0, nfc->regs + nfc->cfg->dma_cfg_off);
|
|
writel(FLCTL_RST, nfc->regs + nfc->cfg->flctl_off);
|
|
}
|
|
|
|
static int rk_nfc_enable_clks(struct udevice *dev, struct rk_nfc *nfc)
|
|
{
|
|
int ret;
|
|
|
|
if (!IS_ERR(nfc->nfc_clk)) {
|
|
ret = clk_prepare_enable(nfc->nfc_clk);
|
|
if (ret)
|
|
dev_err(dev, "failed to enable NFC clk\n");
|
|
}
|
|
|
|
ret = clk_prepare_enable(nfc->ahb_clk);
|
|
if (ret) {
|
|
dev_err(dev, "failed to enable ahb clk\n");
|
|
if (!IS_ERR(nfc->nfc_clk))
|
|
clk_disable_unprepare(nfc->nfc_clk);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void rk_nfc_disable_clks(struct rk_nfc *nfc)
|
|
{
|
|
if (!IS_ERR(nfc->nfc_clk))
|
|
clk_disable_unprepare(nfc->nfc_clk);
|
|
clk_disable_unprepare(nfc->ahb_clk);
|
|
}
|
|
|
|
static int rk_nfc_ooblayout_free(struct mtd_info *mtd, int section,
|
|
struct mtd_oob_region *oob_region)
|
|
{
|
|
struct nand_chip *chip = mtd_to_nand(mtd);
|
|
struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
|
|
|
|
if (section)
|
|
return -ERANGE;
|
|
|
|
/*
|
|
* The beginning of the OOB area stores the reserved data for the NFC,
|
|
* the size of the reserved data is NFC_SYS_DATA_SIZE bytes.
|
|
*/
|
|
oob_region->length = rknand->metadata_size - NFC_SYS_DATA_SIZE - 2;
|
|
oob_region->offset = NFC_SYS_DATA_SIZE + 2;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rk_nfc_ooblayout_ecc(struct mtd_info *mtd, int section,
|
|
struct mtd_oob_region *oob_region)
|
|
{
|
|
struct nand_chip *chip = mtd_to_nand(mtd);
|
|
struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip);
|
|
|
|
if (section)
|
|
return -ERANGE;
|
|
|
|
oob_region->length = mtd->oobsize - rknand->metadata_size;
|
|
oob_region->offset = rknand->metadata_size;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct mtd_ooblayout_ops rk_nfc_ooblayout_ops = {
|
|
.rfree = rk_nfc_ooblayout_free,
|
|
.ecc = rk_nfc_ooblayout_ecc,
|
|
};
|
|
|
|
static int rk_nfc_ecc_init(struct rk_nfc *nfc, struct nand_chip *chip)
|
|
{
|
|
const u8 *strengths = nfc->cfg->ecc_strengths;
|
|
struct mtd_info *mtd = nand_to_mtd(chip);
|
|
struct nand_ecc_ctrl *ecc = &chip->ecc;
|
|
u8 max_strength, nfc_max_strength;
|
|
int i;
|
|
|
|
nfc_max_strength = nfc->cfg->ecc_strengths[0];
|
|
/* If optional dt settings not present. */
|
|
if (!ecc->size || !ecc->strength ||
|
|
ecc->strength > nfc_max_strength) {
|
|
chip->ecc.size = 1024;
|
|
ecc->steps = mtd->writesize / ecc->size;
|
|
|
|
/*
|
|
* HW ECC always requests the number of ECC bytes per 1024 byte
|
|
* blocks. The first 4 OOB bytes are reserved for sys data.
|
|
*/
|
|
max_strength = ((mtd->oobsize / ecc->steps) - 4) * 8 /
|
|
fls(8 * 1024);
|
|
if (max_strength > nfc_max_strength)
|
|
max_strength = nfc_max_strength;
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
if (max_strength >= strengths[i])
|
|
break;
|
|
}
|
|
|
|
if (i >= 4) {
|
|
dev_err(nfc->dev, "unsupported ECC strength\n");
|
|
return -EOPNOTSUPP;
|
|
}
|
|
|
|
ecc->strength = strengths[i];
|
|
}
|
|
ecc->steps = mtd->writesize / ecc->size;
|
|
ecc->bytes = DIV_ROUND_UP(ecc->strength * fls(8 * chip->ecc.size), 8);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rk_nfc_nand_chip_init(ofnode node, struct rk_nfc *nfc, int devnum)
|
|
{
|
|
struct rk_nfc_nand_chip *rknand;
|
|
struct udevice *dev = nfc->dev;
|
|
struct nand_ecc_ctrl *ecc;
|
|
struct nand_chip *chip;
|
|
struct mtd_info *mtd;
|
|
u32 cs[NFC_MAX_NSELS];
|
|
int nsels, i, ret;
|
|
u32 tmp;
|
|
|
|
if (!ofnode_get_property(node, "reg", &nsels))
|
|
return -ENODEV;
|
|
nsels /= sizeof(u32);
|
|
if (!nsels || nsels > NFC_MAX_NSELS) {
|
|
dev_err(dev, "invalid reg property size %d\n", nsels);
|
|
return -EINVAL;
|
|
}
|
|
|
|
rknand = kzalloc(sizeof(*rknand) + nsels * sizeof(u8), GFP_KERNEL);
|
|
if (!rknand)
|
|
return -ENOMEM;
|
|
|
|
rknand->nsels = nsels;
|
|
rknand->timing = nfc->cur_timing;
|
|
|
|
ret = ofnode_read_u32_array(node, "reg", cs, nsels);
|
|
if (ret < 0) {
|
|
dev_err(dev, "Could not retrieve reg property\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
for (i = 0; i < nsels; i++) {
|
|
if (cs[i] >= NFC_MAX_NSELS) {
|
|
dev_err(dev, "invalid CS: %u\n", cs[i]);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (test_and_set_bit(cs[i], &nfc->assigned_cs)) {
|
|
dev_err(dev, "CS %u already assigned\n", cs[i]);
|
|
return -EINVAL;
|
|
}
|
|
|
|
rknand->sels[i] = cs[i];
|
|
}
|
|
|
|
chip = &rknand->chip;
|
|
ecc = &chip->ecc;
|
|
ecc->mode = NAND_ECC_HW_SYNDROME;
|
|
|
|
ret = ofnode_read_u32(node, "nand-ecc-strength", &tmp);
|
|
ecc->strength = ret ? 0 : tmp;
|
|
|
|
ret = ofnode_read_u32(node, "nand-ecc-step-size", &tmp);
|
|
ecc->size = ret ? 0 : tmp;
|
|
|
|
mtd = nand_to_mtd(chip);
|
|
mtd->owner = THIS_MODULE;
|
|
mtd->dev->parent = dev;
|
|
|
|
nand_set_controller_data(chip, nfc);
|
|
|
|
chip->chip_delay = NFC_RB_DELAY_US;
|
|
chip->select_chip = rk_nfc_select_chip;
|
|
chip->cmd_ctrl = rk_nfc_cmd;
|
|
chip->read_buf = rk_nfc_read_buf;
|
|
chip->write_buf = rk_nfc_write_buf;
|
|
chip->read_byte = rockchip_nand_read_byte;
|
|
chip->dev_ready = rockchip_nand_dev_ready;
|
|
chip->controller = &nfc->controller;
|
|
|
|
chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
|
|
chip->options |= NAND_NO_SUBPAGE_WRITE | NAND_USE_BOUNCE_BUFFER;
|
|
|
|
mtd_set_ooblayout(mtd, &rk_nfc_ooblayout_ops);
|
|
rk_nfc_hw_init(nfc);
|
|
ret = nand_scan_ident(mtd, nsels, NULL);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = rk_nfc_ecc_init(nfc, chip);
|
|
if (ret) {
|
|
dev_err(dev, "rk_nfc_ecc_init failed: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = ofnode_read_u32(node, "rockchip,boot-blks", &tmp);
|
|
rknand->boot_blks = ret ? 0 : tmp;
|
|
|
|
ret = ofnode_read_u32(node, "rockchip,boot-ecc-strength", &tmp);
|
|
rknand->boot_ecc = ret ? ecc->strength : tmp;
|
|
|
|
rknand->metadata_size = NFC_SYS_DATA_SIZE * ecc->steps;
|
|
|
|
if (rknand->metadata_size < NFC_SYS_DATA_SIZE + 2) {
|
|
dev_err(dev,
|
|
"driver needs at least %d bytes of meta data\n",
|
|
NFC_SYS_DATA_SIZE + 2);
|
|
return -EIO;
|
|
}
|
|
|
|
if (!nfc->page_buf) {
|
|
nfc->page_buf = kzalloc(NFC_MAX_PAGE_SIZE, GFP_KERNEL);
|
|
if (!nfc->page_buf)
|
|
return -ENOMEM;
|
|
}
|
|
|
|
if (!nfc->oob_buf) {
|
|
nfc->oob_buf = kzalloc(NFC_MAX_OOB_SIZE, GFP_KERNEL);
|
|
if (!nfc->oob_buf) {
|
|
kfree(nfc->page_buf);
|
|
nfc->page_buf = NULL;
|
|
return -ENOMEM;
|
|
}
|
|
}
|
|
|
|
ecc->read_page = rk_nfc_read_page_hwecc;
|
|
ecc->read_page_raw = rk_nfc_read_page_raw;
|
|
ecc->read_oob = rk_nfc_read_oob;
|
|
ecc->write_page = rk_nfc_write_page_hwecc;
|
|
ecc->write_page_raw = rk_nfc_write_page_raw;
|
|
ecc->write_oob = rk_nfc_write_oob;
|
|
|
|
ret = nand_scan_tail(mtd);
|
|
if (ret) {
|
|
dev_err(dev, "nand_scan_tail failed: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
return nand_register(devnum, mtd);
|
|
}
|
|
|
|
static int rk_nfc_nand_chips_init(struct udevice *dev, struct rk_nfc *nfc)
|
|
{
|
|
int ret, i = 0;
|
|
ofnode child;
|
|
|
|
ofnode_for_each_subnode(child, dev_ofnode(dev)) {
|
|
ret = rk_nfc_nand_chip_init(child, nfc, i++);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct nfc_cfg nfc_v6_cfg = {
|
|
.type = NFC_V6,
|
|
.ecc_strengths = {60, 40, 24, 16},
|
|
.ecc_cfgs = {
|
|
0x00040011, 0x00040001, 0x00000011, 0x00000001,
|
|
},
|
|
.flctl_off = 0x08,
|
|
.bchctl_off = 0x0C,
|
|
.dma_cfg_off = 0x10,
|
|
.dma_data_buf_off = 0x14,
|
|
.dma_oob_buf_off = 0x18,
|
|
.dma_st_off = 0x1C,
|
|
.bch_st_off = 0x20,
|
|
.randmz_off = 0x150,
|
|
.int_en_off = 0x16C,
|
|
.int_clr_off = 0x170,
|
|
.int_st_off = 0x174,
|
|
.oob0_off = 0x200,
|
|
.oob1_off = 0x230,
|
|
.ecc0 = {
|
|
.err_flag_bit = 2,
|
|
.low = 3,
|
|
.low_mask = 0x1F,
|
|
.low_bn = 5,
|
|
.high = 27,
|
|
.high_mask = 0x1,
|
|
},
|
|
.ecc1 = {
|
|
.err_flag_bit = 15,
|
|
.low = 16,
|
|
.low_mask = 0x1F,
|
|
.low_bn = 5,
|
|
.high = 29,
|
|
.high_mask = 0x1,
|
|
},
|
|
};
|
|
|
|
static struct nfc_cfg nfc_v8_cfg = {
|
|
.type = NFC_V8,
|
|
.ecc_strengths = {16, 16, 16, 16},
|
|
.ecc_cfgs = {
|
|
0x00000001, 0x00000001, 0x00000001, 0x00000001,
|
|
},
|
|
.flctl_off = 0x08,
|
|
.bchctl_off = 0x0C,
|
|
.dma_cfg_off = 0x10,
|
|
.dma_data_buf_off = 0x14,
|
|
.dma_oob_buf_off = 0x18,
|
|
.dma_st_off = 0x1C,
|
|
.bch_st_off = 0x20,
|
|
.randmz_off = 0x150,
|
|
.int_en_off = 0x16C,
|
|
.int_clr_off = 0x170,
|
|
.int_st_off = 0x174,
|
|
.oob0_off = 0x200,
|
|
.oob1_off = 0x230,
|
|
.ecc0 = {
|
|
.err_flag_bit = 2,
|
|
.low = 3,
|
|
.low_mask = 0x1F,
|
|
.low_bn = 5,
|
|
.high = 27,
|
|
.high_mask = 0x1,
|
|
},
|
|
.ecc1 = {
|
|
.err_flag_bit = 15,
|
|
.low = 16,
|
|
.low_mask = 0x1F,
|
|
.low_bn = 5,
|
|
.high = 29,
|
|
.high_mask = 0x1,
|
|
},
|
|
};
|
|
|
|
static struct nfc_cfg nfc_v9_cfg = {
|
|
.type = NFC_V9,
|
|
.ecc_strengths = {70, 60, 40, 16},
|
|
.ecc_cfgs = {
|
|
0x00000001, 0x06000001, 0x04000001, 0x02000001,
|
|
},
|
|
.flctl_off = 0x10,
|
|
.bchctl_off = 0x20,
|
|
.dma_cfg_off = 0x30,
|
|
.dma_data_buf_off = 0x34,
|
|
.dma_oob_buf_off = 0x38,
|
|
.dma_st_off = 0x3C,
|
|
.bch_st_off = 0x150,
|
|
.randmz_off = 0x208,
|
|
.int_en_off = 0x120,
|
|
.int_clr_off = 0x124,
|
|
.int_st_off = 0x128,
|
|
.oob0_off = 0x200,
|
|
.oob1_off = 0x204,
|
|
.ecc0 = {
|
|
.err_flag_bit = 2,
|
|
.low = 3,
|
|
.low_mask = 0x7F,
|
|
.low_bn = 7,
|
|
.high = 0,
|
|
.high_mask = 0x0,
|
|
},
|
|
.ecc1 = {
|
|
.err_flag_bit = 18,
|
|
.low = 19,
|
|
.low_mask = 0x7F,
|
|
.low_bn = 7,
|
|
.high = 0,
|
|
.high_mask = 0x0,
|
|
},
|
|
};
|
|
|
|
static const struct udevice_id rk_nfc_id_table[] = {
|
|
{
|
|
.compatible = "rockchip,px30-nfc",
|
|
.data = (unsigned long)&nfc_v9_cfg
|
|
},
|
|
{
|
|
.compatible = "rockchip,rk2928-nfc",
|
|
.data = (unsigned long)&nfc_v6_cfg
|
|
},
|
|
{
|
|
.compatible = "rockchip,rv1108-nfc",
|
|
.data = (unsigned long)&nfc_v8_cfg
|
|
},
|
|
{
|
|
.compatible = "rockchip,rk3308-nfc",
|
|
.data = (unsigned long)&nfc_v8_cfg
|
|
},
|
|
{ /* sentinel */ }
|
|
};
|
|
|
|
static int rk_nfc_probe(struct udevice *dev)
|
|
{
|
|
struct rk_nfc *nfc = dev_get_priv(dev);
|
|
int ret = 0;
|
|
|
|
nfc->cfg = (void *)dev_get_driver_data(dev);
|
|
nfc->dev = dev;
|
|
|
|
nfc->regs = (void *)dev_read_addr(dev);
|
|
if (IS_ERR(nfc->regs)) {
|
|
ret = PTR_ERR(nfc->regs);
|
|
goto release_nfc;
|
|
}
|
|
|
|
nfc->nfc_clk = devm_clk_get(dev, "nfc");
|
|
if (IS_ERR(nfc->nfc_clk)) {
|
|
dev_dbg(dev, "no NFC clk\n");
|
|
/* Some earlier models, such as rk3066, have no NFC clk. */
|
|
}
|
|
|
|
nfc->ahb_clk = devm_clk_get(dev, "ahb");
|
|
if (IS_ERR(nfc->ahb_clk)) {
|
|
dev_err(dev, "no ahb clk\n");
|
|
ret = PTR_ERR(nfc->ahb_clk);
|
|
goto release_nfc;
|
|
}
|
|
|
|
ret = rk_nfc_enable_clks(dev, nfc);
|
|
if (ret)
|
|
goto release_nfc;
|
|
|
|
spin_lock_init(&nfc->controller.lock);
|
|
init_waitqueue_head(&nfc->controller.wq);
|
|
|
|
rk_nfc_hw_init(nfc);
|
|
|
|
ret = rk_nfc_nand_chips_init(dev, nfc);
|
|
if (ret) {
|
|
dev_err(dev, "failed to init NAND chips\n");
|
|
goto clk_disable;
|
|
}
|
|
return 0;
|
|
|
|
clk_disable:
|
|
rk_nfc_disable_clks(nfc);
|
|
release_nfc:
|
|
return ret;
|
|
}
|
|
|
|
U_BOOT_DRIVER(rockchip_nfc) = {
|
|
.name = "rockchip_nfc",
|
|
.id = UCLASS_MTD,
|
|
.of_match = rk_nfc_id_table,
|
|
.probe = rk_nfc_probe,
|
|
.priv_auto = sizeof(struct rk_nfc),
|
|
};
|
|
|
|
void board_nand_init(void)
|
|
{
|
|
struct udevice *dev;
|
|
int ret;
|
|
|
|
ret = uclass_get_device_by_driver(UCLASS_MTD,
|
|
DM_DRIVER_GET(rockchip_nfc),
|
|
&dev);
|
|
if (ret && ret != -ENODEV)
|
|
log_err("Failed to initialize ROCKCHIP NAND controller. (error %d)\n",
|
|
ret);
|
|
}
|
|
|
|
int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
|
|
{
|
|
struct mtd_info *mtd;
|
|
size_t length = size;
|
|
|
|
mtd = get_nand_dev_by_index(0);
|
|
return nand_read_skip_bad(mtd, offs, &length, NULL, size, (u_char *)dst);
|
|
}
|
|
|
|
void nand_deselect(void) {}
|