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https://github.com/AsahiLinux/u-boot
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2661dfd004
For NAND boot on PH1-LD4, PH1-sLD8, and some other SoCs, the output of the system bus is disabled by default. It must be enabled by software to have access to the system bus. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
58 lines
1.6 KiB
C
58 lines
1.6 KiB
C
/*
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* Copyright (C) 2011-2014 Panasonic Corporation
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* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/sbc-regs.h>
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#include <asm/arch/sg-regs.h>
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void sbc_init(void)
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{
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u32 tmp;
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/* system bus output enable */
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tmp = readl(PC0CTRL);
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tmp &= 0xfffffcff;
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writel(tmp, PC0CTRL);
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#if !defined(CONFIG_SPL_BUILD)
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/* XECS0 : dummy */
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writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
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writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
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writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
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writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
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#endif
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/* XECS1 : boot memory (always boot swap = on) */
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writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
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writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
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writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
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writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
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/* XECS4 : sub memory */
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writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL40);
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writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL41);
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writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL42);
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writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL44);
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/* XECS5 : peripherals */
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writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL50);
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writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL51);
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writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL52);
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writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL54);
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/* base address regsiters */
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writel(0x0000bc01, SBBASE0); /* boot memory */
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writel(0x0900bfff, SBBASE1); /* dummy */
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writel(0x0400bc01, SBBASE4); /* sub memory */
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writel(0x0800bf01, SBBASE5); /* peripherals */
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sg_set_pinsel(134, 16); /* XIRQ6 -> XECS4 */
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sg_set_pinsel(135, 16); /* XIRQ7 -> XECS5 */
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/* dummy read to assure write process */
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readl(SG_PINCTRL(33));
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}
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