mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-11 15:37:23 +00:00
75 lines
1.8 KiB
C
75 lines
1.8 KiB
C
/*
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* Copyright (c) 2011 The Chromium OS Authors.
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* (C) Copyright 2008
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* Graeme Russ, graeme.russ@gmail.com.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <configs/x86-common.h>
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_SYS_COREBOOT
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#define CONFIG_LAST_STAGE_INIT
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#define CONFIG_SYS_EARLY_PCI_INIT
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#define CONFIG_SYS_CAR_ADDR 0x19200000
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#define CONFIG_SYS_CAR_SIZE (16 * 1024)
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
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#define CONFIG_TRACE_EARLY_SIZE (8 << 20)
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#define CONFIG_TRACE_EARLY
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#define CONFIG_TRACE_EARLY_ADDR 0x01400000
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#define CONFIG_BOOTSTAGE
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#define CONFIG_BOOTSTAGE_REPORT
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#define CONFIG_BOOTSTAGE_FDT
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#define CONFIG_CMD_BOOTSTAGE
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/* Place to stash bootstage data from first-stage U-Boot */
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#define CONFIG_BOOTSTAGE_STASH 0x0110f000
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#define CONFIG_BOOTSTAGE_STASH_SIZE 0x7fc
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#define CONFIG_BOOTSTAGE_USER_COUNT 60
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#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \
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PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
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{PCI_VENDOR_ID_INTEL, \
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PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
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{PCI_VENDOR_ID_INTEL, \
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PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
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{PCI_VENDOR_ID_INTEL, \
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PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
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#define CONFIG_X86_SERIAL
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#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
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"stdout=vga,serial,cbmem\0" \
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"stderr=vga,serial,cbmem\0"
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#define CONFIG_CBMEM_CONSOLE
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#define CONFIG_VIDEO_COREBOOT
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#define CONFIG_NR_DRAM_BANKS 4
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#define CONFIG_TRACE
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#define CONFIG_CMD_TRACE
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#define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
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#define CONFIG_BOOTDELAY 2
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#define CONFIG_CROS_EC
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#define CONFIG_CROS_EC_LPC
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#define CONFIG_CMD_CROS_EC
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#define CONFIG_ARCH_EARLY_INIT_R
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#endif /* __CONFIG_H */
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