Dave Liu b4983e16d1 fsl-ddr: use the 1T timing as default configuration ... For light loaded system, we use the 1T timing to gain better memory performance, but for some heavily loaded system, you have to add the 2T timing options to board files. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>		2009-01-23 17:03:14 -06:00
..
config.mk	Move the MPC8560 ADS board under board/freescale.	2007-12-11 22:34:20 -06:00
ddr.c	fsl-ddr: use the 1T timing as default configuration	2009-01-23 17:03:14 -06:00
law.c	85xx: Use CONFIG_SYS_{PCI*,RIO*}_MEM_PHYS for physical address on FSL boards	2009-01-23 17:03:13 -06:00
Makefile	FSL DDR: Convert MPC8560ADS to new DDR code.	2008-08-27 11:43:49 -05:00
mpc8560ads.c	mpc8xxx: LCRR[CLKDIV] is sometimes five bits	2008-12-19 18:20:25 -06:00
tlb.c	85xx: Introduce CONFIG_SYS_PCI*_MEM_VIRT for FSL boards	2009-01-23 17:03:13 -06:00
u-boot.lds	mpc85xx: workaround old binutils bug	2008-08-10 22:41:12 +02:00