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https://github.com/AsahiLinux/u-boot
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e4f09f97c9
Some devices can wake the system from sleep, e.g opening the lid on a clamshell or moving a USB mouse. Add a wake to specify this for USB devices and add the settings for Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org>
135 lines
3.2 KiB
C
135 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 2016 Intel Corporation
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* Copyright 2020 Google LLC
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*
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* Taken from coreboot apl gpe.h
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*/
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#ifndef _ASM_ARCH_GPE_H_
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#define _ASM_ARCH_GPE_H_
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/* bit position in GPE0a_STS register */
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#define GPE0A_PCIE_SCI_STS 0
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#define GPE0A_SWGPE_STS 2
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#define GPE0A_PCIE_WAKE0_STS 3
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#define GPE0A_PUNIT_SCI_STS 4
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#define GPE0A_PCIE_WAKE1_STS 6
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#define GPE0A_PCIE_WAKE2_STS 7
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#define GPE0A_PCIE_WAKE3_STS 8
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#define GPE0A_PCIE_GPE_STS 9
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#define GPE0A_BATLOW_STS 10
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#define GPE0A_CSE_PME_STS 11
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#define GPE0A_XDCI_PME_STS 12
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#define GPE0A_XHCI_PME_STS 13
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#define GPE0A_AVS_PME_STS 14
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#define GPE0A_GPIO_TIER1_SCI_STS 15
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#define GPE0A_SMB_WAK_STS 16
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#define GPE0A_SATA_PME_STS 17
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#define GPE0A_CNVI_PME_STS 18
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/* Group DW0 is reserved in Apollolake */
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/* GPE_63_32 */
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#define GPE0_DW1_00 32
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#define GPE0_DW1_01 33
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#define GPE0_DW1_02 34
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#define GPE0_DW1_03 36
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#define GPE0_DW1_04 36
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#define GPE0_DW1_05 37
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#define GPE0_DW1_06 38
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#define GPE0_DW1_07 39
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#define GPE0_DW1_08 40
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#define GPE0_DW1_09 41
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#define GPE0_DW1_10 42
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#define GPE0_DW1_11 43
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#define GPE0_DW1_12 44
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#define GPE0_DW1_13 45
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#define GPE0_DW1_14 46
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#define GPE0_DW1_15 47
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#define GPE0_DW1_16 48
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#define GPE0_DW1_17 49
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#define GPE0_DW1_18 50
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#define GPE0_DW1_19 51
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#define GPE0_DW1_20 52
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#define GPE0_DW1_21 53
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#define GPE0_DW1_22 54
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#define GPE0_DW1_23 55
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#define GPE0_DW1_24 56
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#define GPE0_DW1_25 57
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#define GPE0_DW1_26 58
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#define GPE0_DW1_27 59
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#define GPE0_DW1_28 60
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#define GPE0_DW1_29 61
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#define GPE0_DW1_30 62
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#define GPE0_DW1_31 63
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/* GPE_95_64 */
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#define GPE0_DW2_00 64
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#define GPE0_DW2_01 65
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#define GPE0_DW2_02 66
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#define GPE0_DW2_03 67
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#define GPE0_DW2_04 68
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#define GPE0_DW2_05 69
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#define GPE0_DW2_06 70
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#define GPE0_DW2_07 71
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#define GPE0_DW2_08 72
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#define GPE0_DW2_09 73
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#define GPE0_DW2_10 74
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#define GPE0_DW2_11 75
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#define GPE0_DW2_12 76
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#define GPE0_DW2_13 77
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#define GPE0_DW2_14 78
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#define GPE0_DW2_15 79
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#define GPE0_DW2_16 80
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#define GPE0_DW2_17 81
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#define GPE0_DW2_18 82
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#define GPE0_DW2_19 83
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#define GPE0_DW2_20 84
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#define GPE0_DW2_21 85
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#define GPE0_DW2_22 86
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#define GPE0_DW2_23 87
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#define GPE0_DW2_24 88
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#define GPE0_DW2_25 89
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#define GPE0_DW2_26 90
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#define GPE0_DW2_27 91
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#define GPE0_DW2_28 92
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#define GPE0_DW2_29 93
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#define GPE0_DW2_30 94
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#define GPE0_DW2_31 95
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/* GPE_127_96 */
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#define GPE0_DW3_00 96
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#define GPE0_DW3_01 97
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#define GPE0_DW3_02 98
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#define GPE0_DW3_03 99
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#define GPE0_DW3_04 100
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#define GPE0_DW3_05 101
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#define GPE0_DW3_06 102
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#define GPE0_DW3_07 103
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#define GPE0_DW3_08 104
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#define GPE0_DW3_09 105
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#define GPE0_DW3_10 106
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#define GPE0_DW3_11 107
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#define GPE0_DW3_12 108
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#define GPE0_DW3_13 109
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#define GPE0_DW3_14 110
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#define GPE0_DW3_15 111
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#define GPE0_DW3_16 112
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#define GPE0_DW3_17 113
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#define GPE0_DW3_18 114
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#define GPE0_DW3_19 115
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#define GPE0_DW3_20 116
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#define GPE0_DW3_21 117
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#define GPE0_DW3_22 118
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#define GPE0_DW3_23 119
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#define GPE0_DW3_24 120
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#define GPE0_DW3_25 121
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#define GPE0_DW3_26 122
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#define GPE0_DW3_27 123
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#define GPE0_DW3_28 124
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#define GPE0_DW3_29 125
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#define GPE0_DW3_30 126
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#define GPE0_DW3_31 127
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#define GPE_MAX GPE0_DW3_31
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#endif
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