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339613eba5
These two routines are internal to pch_gbe driver. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
503 lines
13 KiB
C
503 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*
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* Intel Platform Controller Hub EG20T (codename Topcliff) GMAC Driver
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <pci.h>
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#include <miiphy.h>
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#include "pch_gbe.h"
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#if !defined(CONFIG_PHYLIB)
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# error "PCH Gigabit Ethernet driver requires PHYLIB - missing CONFIG_PHYLIB"
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#endif
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static struct pci_device_id supported[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_GBE) },
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{ }
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};
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static void pch_gbe_mac_read(struct pch_gbe_regs *mac_regs, u8 *addr)
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{
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u32 macid_hi, macid_lo;
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macid_hi = readl(&mac_regs->mac_adr[0].high);
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macid_lo = readl(&mac_regs->mac_adr[0].low) & 0xffff;
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debug("pch_gbe: macid_hi %#x macid_lo %#x\n", macid_hi, macid_lo);
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addr[0] = (u8)(macid_hi & 0xff);
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addr[1] = (u8)((macid_hi >> 8) & 0xff);
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addr[2] = (u8)((macid_hi >> 16) & 0xff);
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addr[3] = (u8)((macid_hi >> 24) & 0xff);
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addr[4] = (u8)(macid_lo & 0xff);
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addr[5] = (u8)((macid_lo >> 8) & 0xff);
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}
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static int pch_gbe_mac_write(struct pch_gbe_regs *mac_regs, u8 *addr)
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{
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u32 macid_hi, macid_lo;
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ulong start;
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macid_hi = addr[0] + (addr[1] << 8) + (addr[2] << 16) + (addr[3] << 24);
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macid_lo = addr[4] + (addr[5] << 8);
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writel(macid_hi, &mac_regs->mac_adr[0].high);
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writel(macid_lo, &mac_regs->mac_adr[0].low);
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writel(0xfffe, &mac_regs->addr_mask);
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start = get_timer(0);
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while (get_timer(start) < PCH_GBE_TIMEOUT) {
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if (!(readl(&mac_regs->addr_mask) & PCH_GBE_BUSY))
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return 0;
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udelay(10);
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}
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return -ETIME;
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}
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static int pch_gbe_reset(struct udevice *dev)
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{
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struct pch_gbe_priv *priv = dev_get_priv(dev);
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struct eth_pdata *plat = dev_get_platdata(dev);
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struct pch_gbe_regs *mac_regs = priv->mac_regs;
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ulong start;
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priv->rx_idx = 0;
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priv->tx_idx = 0;
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writel(PCH_GBE_ALL_RST, &mac_regs->reset);
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/*
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* Configure the MAC to RGMII mode after reset
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*
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* For some unknown reason, we must do the configuration here right
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* after resetting the whole MAC, otherwise the reset bit in the RESET
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* register will never be cleared by the hardware. And there is another
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* way of having the same magic, that is to configure the MODE register
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* to have the MAC work in MII/GMII mode, which is how current Linux
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* pch_gbe driver does. Since anyway we need program the MAC to RGMII
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* mode in the driver, we just do it here.
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*
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* Note: this behavior is not documented in the hardware manual.
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*/
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writel(PCH_GBE_RGMII_MODE_RGMII | PCH_GBE_CHIP_TYPE_INTERNAL,
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&mac_regs->rgmii_ctrl);
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start = get_timer(0);
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while (get_timer(start) < PCH_GBE_TIMEOUT) {
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if (!(readl(&mac_regs->reset) & PCH_GBE_ALL_RST)) {
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/*
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* Soft reset clears hardware MAC address registers,
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* so we have to reload MAC address here in order to
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* make linux pch_gbe driver happy.
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*/
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return pch_gbe_mac_write(mac_regs, plat->enetaddr);
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}
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udelay(10);
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}
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debug("pch_gbe: reset timeout\n");
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return -ETIME;
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}
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static void pch_gbe_rx_descs_init(struct udevice *dev)
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{
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struct pch_gbe_priv *priv = dev_get_priv(dev);
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struct pch_gbe_regs *mac_regs = priv->mac_regs;
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struct pch_gbe_rx_desc *rx_desc = &priv->rx_desc[0];
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int i;
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memset(rx_desc, 0, sizeof(struct pch_gbe_rx_desc) * PCH_GBE_DESC_NUM);
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for (i = 0; i < PCH_GBE_DESC_NUM; i++)
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rx_desc[i].buffer_addr = dm_pci_virt_to_mem(priv->dev,
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priv->rx_buff[i]);
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flush_dcache_range((ulong)rx_desc, (ulong)&rx_desc[PCH_GBE_DESC_NUM]);
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writel(dm_pci_virt_to_mem(priv->dev, rx_desc),
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&mac_regs->rx_dsc_base);
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writel(sizeof(struct pch_gbe_rx_desc) * (PCH_GBE_DESC_NUM - 1),
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&mac_regs->rx_dsc_size);
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writel(dm_pci_virt_to_mem(priv->dev, rx_desc + 1),
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&mac_regs->rx_dsc_sw_p);
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}
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static void pch_gbe_tx_descs_init(struct udevice *dev)
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{
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struct pch_gbe_priv *priv = dev_get_priv(dev);
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struct pch_gbe_regs *mac_regs = priv->mac_regs;
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struct pch_gbe_tx_desc *tx_desc = &priv->tx_desc[0];
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memset(tx_desc, 0, sizeof(struct pch_gbe_tx_desc) * PCH_GBE_DESC_NUM);
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flush_dcache_range((ulong)tx_desc, (ulong)&tx_desc[PCH_GBE_DESC_NUM]);
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writel(dm_pci_virt_to_mem(priv->dev, tx_desc),
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&mac_regs->tx_dsc_base);
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writel(sizeof(struct pch_gbe_tx_desc) * (PCH_GBE_DESC_NUM - 1),
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&mac_regs->tx_dsc_size);
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writel(dm_pci_virt_to_mem(priv->dev, tx_desc + 1),
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&mac_regs->tx_dsc_sw_p);
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}
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static void pch_gbe_adjust_link(struct pch_gbe_regs *mac_regs,
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struct phy_device *phydev)
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{
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if (!phydev->link) {
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printf("%s: No link.\n", phydev->dev->name);
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return;
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}
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clrbits_le32(&mac_regs->rgmii_ctrl,
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PCH_GBE_RGMII_RATE_2_5M | PCH_GBE_CRS_SEL);
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clrbits_le32(&mac_regs->mode,
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PCH_GBE_MODE_GMII_ETHER | PCH_GBE_MODE_FULL_DUPLEX);
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switch (phydev->speed) {
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case 1000:
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setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_125M);
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setbits_le32(&mac_regs->mode, PCH_GBE_MODE_GMII_ETHER);
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break;
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case 100:
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setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_25M);
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setbits_le32(&mac_regs->mode, PCH_GBE_MODE_MII_ETHER);
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break;
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case 10:
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setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_2_5M);
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setbits_le32(&mac_regs->mode, PCH_GBE_MODE_MII_ETHER);
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break;
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}
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if (phydev->duplex) {
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setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_CRS_SEL);
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setbits_le32(&mac_regs->mode, PCH_GBE_MODE_FULL_DUPLEX);
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}
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printf("Speed: %d, %s duplex\n", phydev->speed,
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(phydev->duplex) ? "full" : "half");
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return;
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}
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static int pch_gbe_start(struct udevice *dev)
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{
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struct pch_gbe_priv *priv = dev_get_priv(dev);
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struct pch_gbe_regs *mac_regs = priv->mac_regs;
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if (pch_gbe_reset(dev))
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return -1;
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pch_gbe_rx_descs_init(dev);
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pch_gbe_tx_descs_init(dev);
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/* Enable frame bursting */
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writel(PCH_GBE_MODE_FR_BST, &mac_regs->mode);
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/* Disable TCP/IP accelerator */
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writel(PCH_GBE_RX_TCPIPACC_OFF, &mac_regs->tcpip_acc);
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/* Disable RX flow control */
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writel(0, &mac_regs->rx_fctrl);
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/* Configure RX/TX mode */
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writel(PCH_GBE_RH_ALM_EMP_16 | PCH_GBE_RH_ALM_FULL_16 |
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PCH_GBE_RH_RD_TRG_32, &mac_regs->rx_mode);
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writel(PCH_GBE_TM_TH_TX_STRT_32 | PCH_GBE_TM_TH_ALM_EMP_16 |
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PCH_GBE_TM_TH_ALM_FULL_32 | PCH_GBE_TM_ST_AND_FD |
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PCH_GBE_TM_SHORT_PKT, &mac_regs->tx_mode);
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/* Start up the PHY */
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if (phy_startup(priv->phydev)) {
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printf("Could not initialize PHY %s\n",
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priv->phydev->dev->name);
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return -1;
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}
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pch_gbe_adjust_link(mac_regs, priv->phydev);
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if (!priv->phydev->link)
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return -1;
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/* Enable TX & RX */
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writel(PCH_GBE_RX_DMA_EN | PCH_GBE_TX_DMA_EN, &mac_regs->dma_ctrl);
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writel(PCH_GBE_MRE_MAC_RX_EN, &mac_regs->mac_rx_en);
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return 0;
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}
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static void pch_gbe_stop(struct udevice *dev)
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{
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struct pch_gbe_priv *priv = dev_get_priv(dev);
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pch_gbe_reset(dev);
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phy_shutdown(priv->phydev);
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}
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static int pch_gbe_send(struct udevice *dev, void *packet, int length)
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{
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struct pch_gbe_priv *priv = dev_get_priv(dev);
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struct pch_gbe_regs *mac_regs = priv->mac_regs;
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struct pch_gbe_tx_desc *tx_head, *tx_desc;
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u16 frame_ctrl = 0;
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u32 int_st;
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ulong start;
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flush_dcache_range((ulong)packet, (ulong)packet + length);
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tx_head = &priv->tx_desc[0];
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tx_desc = &priv->tx_desc[priv->tx_idx];
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if (length < 64)
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frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
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tx_desc->buffer_addr = dm_pci_virt_to_mem(priv->dev, packet);
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tx_desc->length = length;
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tx_desc->tx_words_eob = length + 3;
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tx_desc->tx_frame_ctrl = frame_ctrl;
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tx_desc->dma_status = 0;
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tx_desc->gbec_status = 0;
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flush_dcache_range((ulong)tx_desc, (ulong)&tx_desc[1]);
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/* Test the wrap-around condition */
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if (++priv->tx_idx >= PCH_GBE_DESC_NUM)
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priv->tx_idx = 0;
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writel(dm_pci_virt_to_mem(priv->dev, tx_head + priv->tx_idx),
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&mac_regs->tx_dsc_sw_p);
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start = get_timer(0);
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while (get_timer(start) < PCH_GBE_TIMEOUT) {
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int_st = readl(&mac_regs->int_st);
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if (int_st & PCH_GBE_INT_TX_CMPLT)
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return 0;
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udelay(10);
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}
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debug("pch_gbe: sent failed\n");
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return -ETIME;
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}
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static int pch_gbe_recv(struct udevice *dev, int flags, uchar **packetp)
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{
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struct pch_gbe_priv *priv = dev_get_priv(dev);
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struct pch_gbe_regs *mac_regs = priv->mac_regs;
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struct pch_gbe_rx_desc *rx_desc;
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ulong hw_desc, length;
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void *buffer;
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rx_desc = &priv->rx_desc[priv->rx_idx];
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readl(&mac_regs->int_st);
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hw_desc = readl(&mac_regs->rx_dsc_hw_p_hld);
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/* Just return if not receiving any packet */
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if (virt_to_phys(rx_desc) == hw_desc)
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return -EAGAIN;
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/* Invalidate the descriptor */
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invalidate_dcache_range((ulong)rx_desc, (ulong)&rx_desc[1]);
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length = rx_desc->rx_words_eob - 3 - ETH_FCS_LEN;
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buffer = dm_pci_mem_to_virt(priv->dev, rx_desc->buffer_addr, length, 0);
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invalidate_dcache_range((ulong)buffer, (ulong)buffer + length);
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*packetp = (uchar *)buffer;
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return length;
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}
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static int pch_gbe_free_pkt(struct udevice *dev, uchar *packet, int length)
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{
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struct pch_gbe_priv *priv = dev_get_priv(dev);
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struct pch_gbe_regs *mac_regs = priv->mac_regs;
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struct pch_gbe_rx_desc *rx_head = &priv->rx_desc[0];
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int rx_swp;
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/* Test the wrap-around condition */
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if (++priv->rx_idx >= PCH_GBE_DESC_NUM)
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priv->rx_idx = 0;
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rx_swp = priv->rx_idx;
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if (++rx_swp >= PCH_GBE_DESC_NUM)
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rx_swp = 0;
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writel(dm_pci_virt_to_mem(priv->dev, rx_head + rx_swp),
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&mac_regs->rx_dsc_sw_p);
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return 0;
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}
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static int pch_gbe_mdio_ready(struct pch_gbe_regs *mac_regs)
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{
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ulong start = get_timer(0);
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while (get_timer(start) < PCH_GBE_TIMEOUT) {
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if (readl(&mac_regs->miim) & PCH_GBE_MIIM_OPER_READY)
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return 0;
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udelay(10);
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}
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return -ETIME;
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}
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static int pch_gbe_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
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{
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struct pch_gbe_regs *mac_regs = bus->priv;
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u32 miim;
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if (pch_gbe_mdio_ready(mac_regs))
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return -ETIME;
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miim = (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
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(reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
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PCH_GBE_MIIM_OPER_READ;
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writel(miim, &mac_regs->miim);
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if (pch_gbe_mdio_ready(mac_regs))
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return -ETIME;
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return readl(&mac_regs->miim) & 0xffff;
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}
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static int pch_gbe_mdio_write(struct mii_dev *bus, int addr, int devad,
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int reg, u16 val)
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{
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struct pch_gbe_regs *mac_regs = bus->priv;
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u32 miim;
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if (pch_gbe_mdio_ready(mac_regs))
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return -ETIME;
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miim = (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
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(reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
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PCH_GBE_MIIM_OPER_WRITE | val;
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writel(miim, &mac_regs->miim);
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if (pch_gbe_mdio_ready(mac_regs))
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return -ETIME;
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else
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return 0;
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}
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static int pch_gbe_mdio_init(const char *name, struct pch_gbe_regs *mac_regs)
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{
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struct mii_dev *bus;
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bus = mdio_alloc();
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if (!bus) {
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debug("pch_gbe: failed to allocate MDIO bus\n");
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return -ENOMEM;
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}
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bus->read = pch_gbe_mdio_read;
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bus->write = pch_gbe_mdio_write;
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strcpy(bus->name, name);
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bus->priv = (void *)mac_regs;
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return mdio_register(bus);
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}
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static int pch_gbe_phy_init(struct udevice *dev)
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{
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struct pch_gbe_priv *priv = dev_get_priv(dev);
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struct eth_pdata *plat = dev_get_platdata(dev);
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struct phy_device *phydev;
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int mask = 0xffffffff;
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phydev = phy_find_by_mask(priv->bus, mask, plat->phy_interface);
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if (!phydev) {
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printf("pch_gbe: cannot find the phy\n");
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return -1;
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}
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phy_connect_dev(phydev, dev);
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phydev->supported &= PHY_GBIT_FEATURES;
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phydev->advertising = phydev->supported;
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priv->phydev = phydev;
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phy_config(phydev);
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return 0;
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}
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static int pch_gbe_probe(struct udevice *dev)
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{
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struct pch_gbe_priv *priv;
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struct eth_pdata *plat = dev_get_platdata(dev);
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void *iobase;
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int err;
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/*
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* The priv structure contains the descriptors and frame buffers which
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* need a strict buswidth alignment (64 bytes). This is guaranteed by
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* DM_FLAG_ALLOC_PRIV_DMA flag in the U_BOOT_DRIVER.
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*/
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priv = dev_get_priv(dev);
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priv->dev = dev;
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iobase = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_1, PCI_REGION_MEM);
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plat->iobase = (ulong)iobase;
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priv->mac_regs = (struct pch_gbe_regs *)iobase;
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/* Read MAC address from SROM and initialize dev->enetaddr with it */
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pch_gbe_mac_read(priv->mac_regs, plat->enetaddr);
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plat->phy_interface = PHY_INTERFACE_MODE_RGMII;
|
|
pch_gbe_mdio_init(dev->name, priv->mac_regs);
|
|
priv->bus = miiphy_get_dev_by_name(dev->name);
|
|
|
|
err = pch_gbe_reset(dev);
|
|
if (err)
|
|
return err;
|
|
|
|
return pch_gbe_phy_init(dev);
|
|
}
|
|
|
|
static int pch_gbe_remove(struct udevice *dev)
|
|
{
|
|
struct pch_gbe_priv *priv = dev_get_priv(dev);
|
|
|
|
free(priv->phydev);
|
|
mdio_unregister(priv->bus);
|
|
mdio_free(priv->bus);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct eth_ops pch_gbe_ops = {
|
|
.start = pch_gbe_start,
|
|
.send = pch_gbe_send,
|
|
.recv = pch_gbe_recv,
|
|
.free_pkt = pch_gbe_free_pkt,
|
|
.stop = pch_gbe_stop,
|
|
};
|
|
|
|
static const struct udevice_id pch_gbe_ids[] = {
|
|
{ .compatible = "intel,pch-gbe" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(eth_pch_gbe) = {
|
|
.name = "pch_gbe",
|
|
.id = UCLASS_ETH,
|
|
.of_match = pch_gbe_ids,
|
|
.probe = pch_gbe_probe,
|
|
.remove = pch_gbe_remove,
|
|
.ops = &pch_gbe_ops,
|
|
.priv_auto_alloc_size = sizeof(struct pch_gbe_priv),
|
|
.platdata_auto_alloc_size = sizeof(struct eth_pdata),
|
|
.flags = DM_FLAG_ALLOC_PRIV_DMA,
|
|
};
|
|
|
|
U_BOOT_PCI_DEVICE(eth_pch_gbe, supported);
|