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https://github.com/AsahiLinux/u-boot
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49191d259f
This adds a clock driver to support the GEMGXL management IP block found in FU540 SoCs to control GEM TX clock operation mode for 10/100/1000 Mbps. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Tested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
60 lines
1.4 KiB
C
60 lines
1.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019, Bin Meng <bmeng.cn@gmail.com>
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <asm/io.h>
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struct gemgxl_mgmt_regs {
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__u32 tx_clk_sel;
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};
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struct gemgxl_mgmt_platdata {
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struct gemgxl_mgmt_regs *regs;
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};
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static int gemgxl_mgmt_ofdata_to_platdata(struct udevice *dev)
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{
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struct gemgxl_mgmt_platdata *plat = dev_get_platdata(dev);
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plat->regs = (struct gemgxl_mgmt_regs *)dev_read_addr(dev);
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return 0;
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}
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static ulong gemgxl_mgmt_set_rate(struct clk *clk, ulong rate)
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{
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struct gemgxl_mgmt_platdata *plat = dev_get_platdata(clk->dev);
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/*
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* GEMGXL TX clock operation mode:
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*
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* 0 = GMII mode. Use 125 MHz gemgxlclk from PRCI in TX logic
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* and output clock on GMII output signal GTX_CLK
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* 1 = MII mode. Use MII input signal TX_CLK in TX logic
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*/
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writel(rate != 125000000, &plat->regs->tx_clk_sel);
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return 0;
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}
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const struct clk_ops gemgxl_mgmt_ops = {
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.set_rate = gemgxl_mgmt_set_rate,
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};
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static const struct udevice_id gemgxl_mgmt_match[] = {
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{ .compatible = "sifive,cadencegemgxlmgmt0", },
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(sifive_gemgxl_mgmt) = {
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.name = "sifive-gemgxl-mgmt",
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.id = UCLASS_CLK,
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.of_match = gemgxl_mgmt_match,
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.ofdata_to_platdata = gemgxl_mgmt_ofdata_to_platdata,
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.platdata_auto_alloc_size = sizeof(struct gemgxl_mgmt_platdata),
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.ops = &gemgxl_mgmt_ops,
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};
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