mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-30 08:31:03 +00:00
bf9e3b38f7
* Patch by Josef Baumgartner, 10 Feb 2004: Fixes for Coldfire port * Patch by Brad Kemp, 11 Feb 2004: Fix CFI flash driver problems
316 lines
12 KiB
C
316 lines
12 KiB
C
/*
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* (C) Copyright 2001, 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2002
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* Frank Panno <fpanno@delphintech.com>, Delphin Technology AG
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <ioports.h>
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#include <mpc8260.h>
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#include "ep8260.h"
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/*
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* I/O Port configuration table
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*
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* if conf is 1, then that port pin will be configured at boot time
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* according to the five values podr/pdir/ppar/psor/pdat for that entry
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*/
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const iop_conf_t iop_conf_tab[4][32] = {
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/* Port A configuration */
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{ /* conf ppar psor pdir podr pdat */
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/* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* */
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/* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* */
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/* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* */
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/* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* */
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/* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* */
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/* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* */
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/* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* */
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/* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* */
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/* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* */
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/* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* */
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/* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* */
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/* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* */
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/* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* */
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/* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* */
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/* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* */
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/* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* */
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/* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* */
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/* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* */
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/* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* */
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/* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* */
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/* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* */
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/* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* */
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/* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* */
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/* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* */
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/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
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/* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
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/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
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/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
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/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
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/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
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/* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
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/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
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},
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/* Port B configuration */
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{ /* conf ppar psor pdir podr pdat */
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/* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* */
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/* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* */
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/* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* */
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/* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* */
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/* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* */
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/* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* */
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/* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* */
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/* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* */
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/* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* */
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/* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* */
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/* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* */
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/* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* */
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/* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* */
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/* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* */
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/* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */
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/* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */
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/* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */
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/* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */
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/* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */
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/* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */
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/* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */
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/* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */
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/* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */
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/* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */
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/* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
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/* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */
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/* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */
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/* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */
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/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
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},
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/* Port C */
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{ /* conf ppar psor pdir podr pdat */
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/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
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/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
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/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* */
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/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
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/* PC27 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */
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/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
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/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
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/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
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/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* */
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/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* */
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/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* */
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/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* */
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/* PC19 */ { 0, 1, 0, 0, 0, 0 }, /* */
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/* PC18 */ { 0, 1, 0, 0, 0, 0 }, /* */
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/* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CLK15 */
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/* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CLK16 */
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/* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
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/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* */
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/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
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/* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */
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/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */
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/* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* */
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/* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* */
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/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
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/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
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/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
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/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
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/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
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/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
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/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* */
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/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* */
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/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* */
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},
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/* Port D */
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{ /* conf ppar psor pdir podr pdat */
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/* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* */
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/* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* */
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/* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* */
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/* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
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/* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */
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/* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
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/* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
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/* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
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/* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
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/* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
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/* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
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/* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
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/* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
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/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
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/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* */
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/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* */
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/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
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/* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
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/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
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/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
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/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
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/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
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/* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
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/* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
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/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
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/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
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/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
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/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
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/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
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}
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};
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/* ------------------------------------------------------------------------- */
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/*
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* Setup CS4 to enable the Board Control/Status registers.
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* Otherwise the smcs won't work.
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*/
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int board_early_init_f (void)
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{
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volatile t_ep_regs *regs = (t_ep_regs *) CFG_REGS_BASE;
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile memctl8260_t *memctl = &immap->im_memctl;
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memctl->memc_br4 = CFG_BR4_PRELIM;
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memctl->memc_or4 = CFG_OR4_PRELIM;
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regs->bcsr1 = 0x62; /* to enable terminal on SMC1 */
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regs->bcsr2 = 0x30; /* enable NVRAM and writing FLASH */
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return 0;
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}
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void reset_phy (void)
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{
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volatile t_ep_regs *regs = (t_ep_regs *) CFG_REGS_BASE;
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regs->bcsr4 = 0xC0;
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}
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/*
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* Check Board Identity:
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* I don' know, how the next board revisions will be coded.
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* Thats why its a static interpretation ...
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*/
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int checkboard (void)
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{
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volatile t_ep_regs *regs = (t_ep_regs *) CFG_REGS_BASE;
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uint major = 0, minor = 0;
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switch (regs->bcsr0) {
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case 0x02:
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major = 1;
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break;
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case 0x03:
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major = 1;
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minor = 1;
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break;
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default:
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break;
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}
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printf ("Board: Embedded Planet EP8260, Revision %d.%d\n",
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major, minor);
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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long int initdram (int board_type)
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile memctl8260_t *memctl = &immap->im_memctl;
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volatile uchar c = 0;
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volatile uchar *ramaddr = (uchar *) (CFG_SDRAM_BASE) + 0x110;
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/*
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ulong psdmr = CFG_PSDMR;
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#ifdef CFG_LSDRAM
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ulong lsdmr = CFG_LSDMR;
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#endif
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*/
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long size = CFG_SDRAM0_SIZE;
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int i;
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/*
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* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
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*
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* "At system reset, initialization software must set up the
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* programmable parameters in the memory controller banks registers
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* (ORx, BRx, P/LSDMR). After all memory parameters are configured,
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* system software should execute the following initialization sequence
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* for each SDRAM device.
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*
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* 1. Issue a PRECHARGE-ALL-BANKS command
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* 2. Issue eight CBR REFRESH commands
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* 3. Issue a MODE-SET command to initialize the mode register
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*
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* The initial commands are executed by setting P/LSDMR[OP] and
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* accessing the SDRAM with a single-byte transaction."
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*
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* The appropriate BRx/ORx registers have already been set when we
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* get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
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*/
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memctl->memc_psrt = CFG_PSRT;
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memctl->memc_mptpr = CFG_MPTPR;
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memctl->memc_psdmr = (ulong) CFG_PSDMR | PSDMR_OP_PREA;
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*ramaddr = c;
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memctl->memc_psdmr = (ulong) CFG_PSDMR | PSDMR_OP_CBRR;
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for (i = 0; i < 8; i++)
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*ramaddr = c;
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memctl->memc_psdmr = (ulong) CFG_PSDMR | PSDMR_OP_MRW;
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*ramaddr = c;
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memctl->memc_psdmr = (ulong) CFG_PSDMR | PSDMR_OP_NORM | PSDMR_RFEN;
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*ramaddr = c;
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#ifndef CFG_RAMBOOT
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#ifdef CFG_LSDRAM
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size += CFG_SDRAM1_SIZE;
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ramaddr = (uchar *) (CFG_SDRAM1_BASE) + 0x8c;
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memctl->memc_lsrt = CFG_LSRT;
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memctl->memc_lsdmr = (ulong) CFG_LSDMR | PSDMR_OP_PREA;
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*ramaddr = c;
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memctl->memc_lsdmr = (ulong) CFG_LSDMR | PSDMR_OP_CBRR;
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for (i = 0; i < 8; i++)
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*ramaddr = c;
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memctl->memc_lsdmr = (ulong) CFG_LSDMR | PSDMR_OP_MRW;
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*ramaddr = c;
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memctl->memc_lsdmr = (ulong) CFG_LSDMR | PSDMR_OP_NORM | PSDMR_RFEN;
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*ramaddr = c;
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#endif /* CFG_LSDRAM */
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#endif /* CFG_RAMBOOT */
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return (size * 1024 * 1024);
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}
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