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u-boot/board/freescale/ls1012aqds
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Tom Rini 65cc0e2a65 global: Move remaining CONFIG_SYS_* to CFG_SYS_* 
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do
not easily transition to Kconfig. In many cases they likely should come
from the device tree instead. Move these out of CONFIG namespace and in
to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:06:08 -05:00
..
eth.c global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace 2022-11-10 10:08:55 -05:00
Kconfig nxp: Make board/freescale/common/Kconfig safe to include once in arch/Kconfig 2022-07-05 17:03:02 -04:00
ls1012aqds.c global: Move remaining CONFIG_SYS_* to CFG_SYS_* 2022-12-05 16:06:08 -05:00
ls1012aqds_pfe.h net: freescale: replace usage of phy-mode = "sgmii-2500" with "2500base-x" 2021-09-28 18:50:56 +03:00
ls1012aqds_qixis.h SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
MAINTAINERS board: ls1012aqds: Update MAINTAINERS 2021-03-05 10:25:42 +05:30
Makefile board: freescale: ls1012aqds: enable network support on ls1012aqds 2018-03-22 15:05:29 -05:00
README WS cleanup: remove SPACE(s) followed by TAB 2021-09-30 09:08:16 -04:00

README 

Overview
--------
QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
development platform, with a complete debugging environment.
The LS1012AQDS board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.

LS1012A SoC Overview
--------------------
Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1012A
SoC overview.

LS1012AQDS board Overview
-----------------------
 - SERDES Connections, 4 lanes supporting:
      - PCI Express - 3.0
      - SGMII, SGMII 2.5
      - SATA 3.0
 - DDR Controller
     - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
 - QSPI Controller
     - A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
       signals to QSPI NOR flash memory (2 virtual banks) and the QSPI
       emulator
 - USB 3.0
    - One USB 3.0 controller with integrated PHY
    - One high-speed USB 3.0 port
 - USB 2.0
    - One USB 2.0 controller with ULPI interface
 - Two enhanced secure digital host controllers:
    - SDHC1 controller can be connected to onboard SDHC connector
    - SDHC2 controller: 1-/4-bit SD/MMC card supporting 1.8 V devices
 - 2 I2C controllers
 - One SATA onboard connectors
 - UART
 - 5 SAI
    - One SAI port with audio codec SGTL5000:
	• Provides MIC bias
	• Provides headphone and line output
    - One SAI port terminated at 2x6 header
    - Three SAI Tx/Rx ports terminated at 2x3 headers
 - ARM JTAG support

Booting Options
---------------
a) QSPI Flash Emu Boot
b) QSPI Flash 1
c) QSPI Flash 2

QSPI flash map
--------------
Images		| Size	|QSPI Flash Address
------------------------------------------
RCW + PBI	| 1MB	| 0x4000_0000
U-boot		| 1MB	| 0x4010_0000
U-boot Env	| 1MB	| 0x4020_0000
PPA FIT image	| 2MB	| 0x4050_0000
Linux ITB	| ~53MB | 0x40A0_0000