mirror of
https://github.com/AsahiLinux/u-boot
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270f1fb7b2
Add support for lpuart1, lpuart2 and lpuart3. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
553 lines
15 KiB
Text
553 lines
15 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 NXP
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "fsl-imx8-ca35.dtsi"
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#include <dt-bindings/soc/imx_rsrc.h>
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#include <dt-bindings/soc/imx8_pd.h>
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#include <dt-bindings/clock/imx8qxp-clock.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/pinctrl/pads-imx8qxp.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Freescale i.MX8DX";
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compatible = "fsl,imx8dx", "fsl,imx8qxp";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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ethernet0 = &fec1;
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ethernet1 = &fec2;
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serial0 = &lpuart0;
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mmc0 = &usdhc1;
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mmc1 = &usdhc2;
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mmc2 = &usdhc3;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x00000000 0x80000000 0 0x40000000>;
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/* DRAM space - 1, size : 1 GB DRAM */
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/*
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* reserved-memory layout
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* 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4
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* Shouldn't be used at A core and Linux side.
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*
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*/
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decoder_boot: decoder_boot@0x84000000 {
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no-map;
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reg = <0 0x84000000 0 0x2000000>;
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};
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encoder_boot: encoder_boot@0x86000000 {
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no-map;
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reg = <0 0x86000000 0 0x2000000>;
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};
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rpmsg_reserved: rpmsg@0x90000000 {
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no-map;
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reg = <0 0x90000000 0 0x400000>;
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};
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decoder_rpc: decoder_rpc@0x90400000 {
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no-map;
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reg = <0 0x90400000 0 0x1000000>;
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};
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encoder_rpc: encoder_rpc@0x91400000 {
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no-map;
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reg = <0 0x91400000 0 0x1000000>;
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};
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dsp_reserved: dsp@0x92400000 {
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no-map;
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reg = <0 0x92400000 0 0x2000000>;
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};
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decoder_str: str@0x94400000 {
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no-map;
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reg = <0 0x94400000 0 0x1800000>;
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};
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/* global autoconfigured region for contiguous allocations */
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linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0 0x28000000>;
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alloc-ranges = <0 0x96000000 0 0x28000000>;
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linux,cma-default;
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};
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};
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gic: interrupt-controller@51a00000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
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<0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
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interrupt-parent = <&gic>;
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};
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mu: mu@5d1c0000 {
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compatible = "fsl,imx8-mu";
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reg = <0x0 0x5d1c0000 0x0 0x10000>;
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interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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status = "okay";
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clk: clk {
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compatible = "fsl,imx8qxp-clk";
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#clock-cells = <1>;
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};
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iomuxc: iomuxc {
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compatible = "fsl,imx8qxp-iomuxc";
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};
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};
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imx8qx-pm {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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pd_lsio: PD_LSIO {
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compatible = "nxp,imx8-pd";
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reg = <SC_R_LAST>;
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#power-domain-cells = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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pd_lsio_gpio0: PD_LSIO_GPIO_0 {
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reg = <SC_R_GPIO_0>;
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#power-domain-cells = <0>;
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power-domains = <&pd_lsio>;
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};
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pd_lsio_gpio1: PD_LSIO_GPIO_1 {
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reg = <SC_R_GPIO_1>;
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#power-domain-cells = <0>;
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power-domains = <&pd_lsio>;
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};
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pd_lsio_gpio2: PD_LSIO_GPIO_2 {
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reg = <SC_R_GPIO_2>;
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#power-domain-cells = <0>;
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power-domains = <&pd_lsio>;
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};
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pd_lsio_gpio3: PD_LSIO_GPIO_3 {
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reg = <SC_R_GPIO_3>;
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#power-domain-cells = <0>;
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power-domains = <&pd_lsio>;
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};
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pd_lsio_gpio4: PD_LSIO_GPIO_4 {
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reg = <SC_R_GPIO_4>;
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#power-domain-cells = <0>;
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power-domains = <&pd_lsio>;
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};
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pd_lsio_gpio5: PD_LSIO_GPIO_5{
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reg = <SC_R_GPIO_5>;
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#power-domain-cells = <0>;
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power-domains = <&pd_lsio>;
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};
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pd_lsio_gpio6: PD_LSIO_GPIO_6 {
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reg = <SC_R_GPIO_6>;
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#power-domain-cells = <0>;
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power-domains = <&pd_lsio>;
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};
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pd_lsio_gpio7: PD_LSIO_GPIO_7 {
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reg = <SC_R_GPIO_7>;
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#power-domain-cells = <0>;
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power-domains = <&pd_lsio>;
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};
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};
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pd_conn: PD_CONN {
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compatible = "nxp,imx8-pd";
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reg = <SC_R_LAST>;
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#power-domain-cells = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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pd_conn_sdch0: PD_CONN_SDHC_0 {
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reg = <SC_R_SDHC_0>;
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#power-domain-cells = <0>;
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power-domains = <&pd_conn>;
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};
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pd_conn_sdch1: PD_CONN_SDHC_1 {
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reg = <SC_R_SDHC_1>;
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#power-domain-cells = <0>;
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power-domains = <&pd_conn>;
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};
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pd_conn_sdch2: PD_CONN_SDHC_2 {
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reg = <SC_R_SDHC_2>;
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#power-domain-cells = <0>;
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power-domains = <&pd_conn>;
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};
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pd_conn_enet0: PD_CONN_ENET_0 {
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reg = <SC_R_ENET_0>;
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#power-domain-cells = <0>;
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power-domains = <&pd_conn>;
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};
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pd_conn_enet1: PD_CONN_ENET_1 {
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reg = <SC_R_ENET_1>;
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#power-domain-cells = <0>;
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power-domains = <&pd_conn>;
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};
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};
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pd_dma: PD_DMA {
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compatible = "nxp,imx8-pd";
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reg = <SC_R_LAST>;
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#power-domain-cells = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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pd_dma_lpi2c0: PD_DMA_I2C_0 {
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reg = <SC_R_I2C_0>;
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#power-domain-cells = <0>;
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power-domains = <&pd_dma>;
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};
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pd_dma_lpi2c1: PD_DMA_I2C_1 {
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reg = <SC_R_I2C_1>;
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#power-domain-cells = <0>;
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power-domains = <&pd_dma>;
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};
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pd_dma_lpi2c2:PD_DMA_I2C_2 {
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reg = <SC_R_I2C_2>;
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#power-domain-cells = <0>;
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power-domains = <&pd_dma>;
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};
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pd_dma_lpi2c3: PD_DMA_I2C_3 {
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reg = <SC_R_I2C_3>;
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#power-domain-cells = <0>;
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power-domains = <&pd_dma>;
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};
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pd_dma_lpuart0: PD_DMA_UART0 {
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reg = <SC_R_UART_0>;
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#power-domain-cells = <0>;
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power-domains = <&pd_dma>;
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wakeup-irq = <225>;
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};
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pd_dma_lpuart1: PD_DMA_UART1 {
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reg = <SC_R_UART_1>;
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#power-domain-cells = <0>;
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power-domains = <&pd_dma>;
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};
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pd_dma_lpuart2: PD_DMA_UART2 {
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reg = <SC_R_UART_2>;
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#power-domain-cells = <0>;
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power-domains = <&pd_dma>;
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};
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pd_dma_lpuart3: PD_DMA_UART3 {
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reg = <SC_R_UART_3>;
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#power-domain-cells = <0>;
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power-domains = <&pd_dma>;
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};
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};
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};
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i2c0: i2c@5a800000 {
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compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
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reg = <0x0 0x5a800000 0x0 0x4000>;
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interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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clocks = <&clk IMX8QXP_I2C0_CLK>;
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clock-names = "per";
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assigned-clocks = <&clk IMX8QXP_I2C0_CLK>;
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assigned-clock-rates = <24000000>;
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power-domains = <&pd_dma_lpi2c0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: i2c@5a810000 {
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compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
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reg = <0x0 0x5a810000 0x0 0x4000>;
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interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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clocks = <&clk IMX8QXP_I2C1_CLK>,
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<&clk IMX8QXP_I2C1_IPG_CLK>;
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clock-names = "per", "ipg";
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assigned-clocks = <&clk IMX8QXP_I2C1_CLK>;
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assigned-clock-rates = <24000000>;
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power-domains = <&pd_dma_lpi2c1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c2: i2c@5a820000 {
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compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
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reg = <0x0 0x5a820000 0x0 0x4000>;
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interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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clocks = <&clk IMX8QXP_I2C2_CLK>;
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clock-names = "per";
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assigned-clocks = <&clk IMX8QXP_I2C2_CLK>;
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assigned-clock-rates = <24000000>;
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power-domains = <&pd_dma_lpi2c2>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c3: i2c@5a830000 {
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compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
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reg = <0x0 0x5a830000 0x0 0x4000>;
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interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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clocks = <&clk IMX8QXP_I2C3_CLK>,
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<&clk IMX8QXP_I2C3_IPG_CLK>;
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clock-names = "per", "ipg";
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assigned-clocks = <&clk IMX8QXP_I2C3_CLK>;
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assigned-clock-rates = <24000000>;
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power-domains = <&pd_dma_lpi2c3>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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gpio0: gpio@5d080000 {
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compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
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reg = <0x0 0x5d080000 0x0 0x10000>;
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interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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power-domains = <&pd_lsio_gpio0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio1: gpio@5d090000 {
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compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
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reg = <0x0 0x5d090000 0x0 0x10000>;
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interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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power-domains = <&pd_lsio_gpio1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio@5d0a0000 {
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compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
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reg = <0x0 0x5d0a0000 0x0 0x10000>;
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interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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power-domains = <&pd_lsio_gpio2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio3: gpio@5d0b0000 {
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compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
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reg = <0x0 0x5d0b0000 0x0 0x10000>;
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interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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power-domains = <&pd_lsio_gpio3>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio4: gpio@5d0c0000 {
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compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
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reg = <0x0 0x5d0c0000 0x0 0x10000>;
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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power-domains = <&pd_lsio_gpio4>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio5: gpio@5d0d0000 {
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compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
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reg = <0x0 0x5d0d0000 0x0 0x10000>;
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interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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power-domains = <&pd_lsio_gpio5>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio6: gpio@5d0e0000 {
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compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
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reg = <0x0 0x5d0e0000 0x0 0x10000>;
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interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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power-domains = <&pd_lsio_gpio6>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio7: gpio@5d0f0000 {
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compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
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reg = <0x0 0x5d0f0000 0x0 0x10000>;
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interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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power-domains = <&pd_lsio_gpio7>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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lpuart0: serial@5a060000 {
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compatible = "fsl,imx8qm-lpuart";
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reg = <0x0 0x5a060000 0x0 0x1000>;
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interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8QXP_UART0_CLK>,
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<&clk IMX8QXP_UART0_IPG_CLK>;
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clock-names = "per", "ipg";
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assigned-clocks = <&clk IMX8QXP_UART0_CLK>;
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assigned-clock-rates = <80000000>;
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power-domains = <&pd_dma_lpuart0>;
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status = "disabled";
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};
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lpuart1: serial@5a070000 {
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compatible = "fsl,imx8qm-lpuart";
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reg = <0x0 0x5a070000 0x0 0x1000>;
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interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8QXP_UART1_CLK>,
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<&clk IMX8QXP_UART1_IPG_CLK>;
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clock-names = "per", "ipg";
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assigned-clocks = <&clk IMX8QXP_UART1_CLK>;
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assigned-clock-rates = <80000000>;
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power-domains = <&pd_dma_lpuart1>;
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status = "disabled";
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};
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lpuart2: serial@5a080000 {
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compatible = "fsl,imx8qm-lpuart";
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reg = <0x0 0x5a080000 0x0 0x1000>;
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interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8QXP_UART2_CLK>,
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<&clk IMX8QXP_UART2_IPG_CLK>;
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clock-names = "per", "ipg";
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assigned-clocks = <&clk IMX8QXP_UART2_CLK>;
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assigned-clock-rates = <80000000>;
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power-domains = <&pd_dma_lpuart2>;
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status = "disabled";
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};
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lpuart3: serial@5a090000 {
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compatible = "fsl,imx8qm-lpuart";
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reg = <0x0 0x5a090000 0x0 0x1000>;
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|
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8QXP_UART3_CLK>,
|
|
<&clk IMX8QXP_UART3_IPG_CLK>;
|
|
clock-names = "per", "ipg";
|
|
assigned-clocks = <&clk IMX8QXP_UART3_CLK>;
|
|
assigned-clock-rates = <80000000>;
|
|
power-domains = <&pd_dma_lpuart3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc1: usdhc@5b010000 {
|
|
compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0 0x5b010000 0x0 0x10000>;
|
|
clocks = <&clk IMX8QXP_SDHC0_IPG_CLK>,
|
|
<&clk IMX8QXP_SDHC0_CLK>,
|
|
<&clk IMX8QXP_CLK_DUMMY>;
|
|
clock-names = "ipg", "per", "ahb";
|
|
assigned-clocks = <&clk IMX8QXP_SDHC0_SEL>, <&clk IMX8QXP_SDHC0_DIV>;
|
|
assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>;
|
|
assigned-clock-rates = <0>, <400000000>;
|
|
power-domains = <&pd_conn_sdch0>;
|
|
fsl,tuning-start-tap = <20>;
|
|
fsl,tuning-step= <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc2: usdhc@5b020000 {
|
|
compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0 0x5b020000 0x0 0x10000>;
|
|
clocks = <&clk IMX8QXP_SDHC1_IPG_CLK>,
|
|
<&clk IMX8QXP_SDHC1_CLK>,
|
|
<&clk IMX8QXP_CLK_DUMMY>;
|
|
clock-names = "ipg", "per", "ahb";
|
|
assigned-clocks = <&clk IMX8QXP_SDHC1_SEL>, <&clk IMX8QXP_SDHC1_DIV>;
|
|
assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>;
|
|
assigned-clock-rates = <0>, <200000000>;
|
|
power-domains = <&pd_conn_sdch1>;
|
|
fsl,tuning-start-tap = <20>;
|
|
fsl,tuning-step= <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc3: usdhc@5b030000 {
|
|
compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0 0x5b030000 0x0 0x10000>;
|
|
clocks = <&clk IMX8QXP_SDHC2_IPG_CLK>,
|
|
<&clk IMX8QXP_SDHC2_CLK>,
|
|
<&clk IMX8QXP_CLK_DUMMY>;
|
|
clock-names = "ipg", "per", "ahb";
|
|
assigned-clocks = <&clk IMX8QXP_SDHC2_SEL>, <&clk IMX8QXP_SDHC2_DIV>;
|
|
assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>;
|
|
assigned-clock-rates = <0>, <200000000>;
|
|
power-domains = <&pd_conn_sdch2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
fec1: ethernet@5b040000 {
|
|
compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec";
|
|
reg = <0x0 0x5b040000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8QXP_ENET0_IPG_CLK>, <&clk IMX8QXP_ENET0_AHB_CLK>,
|
|
<&clk IMX8QXP_ENET0_RGMII_TX_CLK>, <&clk IMX8QXP_ENET0_PTP_CLK>;
|
|
clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
|
|
assigned-clocks = <&clk IMX8QXP_ENET0_REF_DIV>, <&clk IMX8QXP_ENET0_PTP_CLK>;
|
|
assigned-clock-rates = <125000000>, <125000000>;
|
|
fsl,num-tx-queues=<3>;
|
|
fsl,num-rx-queues=<3>;
|
|
power-domains = <&pd_conn_enet0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
fec2: ethernet@5b050000 {
|
|
compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec";
|
|
reg = <0x0 0x5b050000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX8QXP_ENET1_IPG_CLK>, <&clk IMX8QXP_ENET1_AHB_CLK>,
|
|
<&clk IMX8QXP_ENET1_RGMII_TX_CLK>, <&clk IMX8QXP_ENET1_PTP_CLK>;
|
|
clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
|
|
assigned-clocks = <&clk IMX8QXP_ENET1_REF_DIV>, <&clk IMX8QXP_ENET1_PTP_CLK>;
|
|
assigned-clock-rates = <125000000>, <125000000>;
|
|
fsl,num-tx-queues=<3>;
|
|
fsl,num-rx-queues=<3>;
|
|
power-domains = <&pd_conn_enet1>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
&A35_0 {
|
|
clocks = <&clk IMX8QXP_A35_DIV>;
|
|
};
|
|
|
|
/delete-node/ &A35_2;
|
|
/delete-node/ &A35_3;
|