mirror of
https://github.com/AsahiLinux/u-boot
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69b19ca67b
Sync k3-j721e DTS with kernel.org v6.6-rc1. * Use mcu_timer0 defined in k3-j721e-mcu-wakeup.dtsi and remove timer0, we have its clocks set up in clk-data now * Remove hbmc node as support is buggy and needs to be fixed * Remove aliases and chosen node, use them from Kernel * Remove /delete-property/ and clock-frequency from sdhci, usbss, and mcu_uart nodes as we have them in clk and dev data * Remove dummy_clocks as they are not needed * Remove cpsw node as it is not required since it has been fixed in U-Boot * Remove pcie nodes, they are not needed * Remove mcu_i2c0 as it is used for tps659413 PMIC in j721e-sk for which support is not yet added * Change secproxy nodes to their Linux definitions * Remove overriding of ti,cluster-mode in MAIN R5 to default to lockstep mode same as Kernel * Retain tps6594 node as TPS6594 PMIC support is still under review in the Kernel [1], cleanup will be taken post its merge [1] https://lore.kernel.org/all/20230810-tps6594-v6-0-2b2e2399e2ef@ti.com/ Signed-off-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
181 lines
2 KiB
Text
181 lines
2 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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*/
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#include "k3-j721e-binman.dtsi"
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&cbass_main {
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bootph-pre-ram;
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};
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&main_navss {
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bootph-pre-ram;
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};
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&cbass_mcu_wakeup {
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bootph-pre-ram;
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chipid@43000014 {
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bootph-pre-ram;
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};
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};
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&mcu_navss {
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bootph-pre-ram;
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};
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&mcu_ringacc {
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bootph-pre-ram;
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};
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&mcu_udmap {
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reg = <0x0 0x285c0000 0x0 0x100>,
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<0x0 0x284c0000 0x0 0x4000>,
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<0x0 0x2a800000 0x0 0x40000>,
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<0x0 0x284a0000 0x0 0x4000>,
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<0x0 0x2aa00000 0x0 0x40000>,
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<0x0 0x28400000 0x0 0x2000>;
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reg-names = "gcfg", "rchan", "rchanrt", "tchan",
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"tchanrt", "rflow";
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bootph-pre-ram;
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};
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&secure_proxy_main {
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bootph-pre-ram;
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};
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&dmsc {
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bootph-pre-ram;
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k3_sysreset: sysreset-controller {
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compatible = "ti,sci-sysreset";
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bootph-pre-ram;
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};
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};
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&k3_pds {
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bootph-pre-ram;
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};
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&k3_clks {
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bootph-pre-ram;
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};
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&k3_reset {
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bootph-pre-ram;
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};
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&wkup_pmx0 {
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bootph-pre-ram;
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};
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&main_pmx0 {
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bootph-pre-ram;
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};
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&main_uart0 {
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bootph-pre-ram;
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};
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&mcu_uart0 {
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bootph-pre-ram;
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};
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&main_sdhci0 {
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bootph-pre-ram;
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};
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&main_sdhci1 {
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bootph-pre-ram;
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};
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&main_uart0_pins_default {
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bootph-pre-ram;
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};
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&main_usbss0_pins_default {
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bootph-pre-ram;
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};
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&usbss0 {
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bootph-pre-ram;
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};
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&usb0 {
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dr_mode = "peripheral";
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bootph-pre-ram;
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};
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&main_mmc1_pins_default {
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bootph-pre-ram;
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};
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&wkup_i2c0_pins_default {
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bootph-pre-ram;
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};
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&wkup_uart0 {
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bootph-pre-ram;
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status = "okay";
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};
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&wkup_i2c0 {
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bootph-pre-ram;
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status = "okay";
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};
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&main_i2c0 {
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bootph-pre-ram;
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};
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&main_i2c0_pins_default {
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bootph-pre-ram;
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};
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&main_esm {
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bootph-pre-ram;
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};
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&exp2 {
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bootph-pre-ram;
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};
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&mcu_fss0_ospi0_pins_default {
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bootph-pre-ram;
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};
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&fss {
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bootph-pre-ram;
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};
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&wkup_gpio0 {
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bootph-pre-ram;
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};
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&ospi0 {
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bootph-pre-ram;
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flash@0 {
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bootph-pre-ram;
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};
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};
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&ospi1 {
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bootph-pre-ram;
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flash@0 {
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bootph-pre-ram;
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};
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};
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&mcu_fss0_hpb0_pins_default {
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bootph-pre-ram;
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};
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&wkup_gpio_pins_default {
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bootph-pre-ram;
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};
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&mcu_fss0_ospi1_pins_default {
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bootph-pre-ram;
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};
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