mirror of
https://github.com/AsahiLinux/u-boot
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
690 lines
18 KiB
C
690 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Atmel DataFlash probing
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*
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* Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
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* Haikun Wang (haikun.wang@freescale.com)
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <spi.h>
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#include <spi_flash.h>
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#include <div64.h>
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#include <linux/err.h>
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#include <linux/math64.h>
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#include "sf_internal.h"
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/* reads can bypass the buffers */
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#define OP_READ_CONTINUOUS 0xE8
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#define OP_READ_PAGE 0xD2
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/* group B requests can run even while status reports "busy" */
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#define OP_READ_STATUS 0xD7 /* group B */
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/* move data between host and buffer */
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#define OP_READ_BUFFER1 0xD4 /* group B */
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#define OP_READ_BUFFER2 0xD6 /* group B */
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#define OP_WRITE_BUFFER1 0x84 /* group B */
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#define OP_WRITE_BUFFER2 0x87 /* group B */
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/* erasing flash */
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#define OP_ERASE_PAGE 0x81
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#define OP_ERASE_BLOCK 0x50
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/* move data between buffer and flash */
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#define OP_TRANSFER_BUF1 0x53
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#define OP_TRANSFER_BUF2 0x55
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#define OP_MREAD_BUFFER1 0xD4
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#define OP_MREAD_BUFFER2 0xD6
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#define OP_MWERASE_BUFFER1 0x83
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#define OP_MWERASE_BUFFER2 0x86
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#define OP_MWRITE_BUFFER1 0x88 /* sector must be pre-erased */
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#define OP_MWRITE_BUFFER2 0x89 /* sector must be pre-erased */
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/* write to buffer, then write-erase to flash */
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#define OP_PROGRAM_VIA_BUF1 0x82
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#define OP_PROGRAM_VIA_BUF2 0x85
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/* compare buffer to flash */
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#define OP_COMPARE_BUF1 0x60
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#define OP_COMPARE_BUF2 0x61
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/* read flash to buffer, then write-erase to flash */
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#define OP_REWRITE_VIA_BUF1 0x58
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#define OP_REWRITE_VIA_BUF2 0x59
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/*
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* newer chips report JEDEC manufacturer and device IDs; chip
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* serial number and OTP bits; and per-sector writeprotect.
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*/
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#define OP_READ_ID 0x9F
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#define OP_READ_SECURITY 0x77
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#define OP_WRITE_SECURITY_REVC 0x9A
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#define OP_WRITE_SECURITY 0x9B /* revision D */
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struct dataflash {
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uint8_t command[16];
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unsigned short page_offset; /* offset in flash address */
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};
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/* Return the status of the DataFlash device */
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static inline int dataflash_status(struct spi_slave *spi)
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{
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int ret;
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u8 status;
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/*
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* NOTE: at45db321c over 25 MHz wants to write
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* a dummy byte after the opcode...
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*/
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ret = spi_flash_cmd(spi, OP_READ_STATUS, &status, 1);
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return ret ? -EIO : status;
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}
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/*
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* Poll the DataFlash device until it is READY.
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* This usually takes 5-20 msec or so; more for sector erase.
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* ready: return > 0
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*/
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static int dataflash_waitready(struct spi_slave *spi)
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{
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int status;
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int timeout = 2 * CONFIG_SYS_HZ;
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int timebase;
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timebase = get_timer(0);
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do {
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status = dataflash_status(spi);
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if (status < 0)
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status = 0;
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if (status & (1 << 7)) /* RDY/nBSY */
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return status;
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mdelay(3);
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} while (get_timer(timebase) < timeout);
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return -ETIME;
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}
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/* Erase pages of flash */
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static int spi_dataflash_erase(struct udevice *dev, u32 offset, size_t len)
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{
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struct dataflash *dataflash;
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struct spi_flash *spi_flash;
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struct spi_slave *spi;
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unsigned blocksize;
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uint8_t *command;
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uint32_t rem;
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int status;
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dataflash = dev_get_priv(dev);
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spi_flash = dev_get_uclass_priv(dev);
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spi = spi_flash->spi;
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blocksize = spi_flash->page_size << 3;
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memset(dataflash->command, 0 , sizeof(dataflash->command));
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command = dataflash->command;
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debug("%s: erase addr=0x%x len 0x%x\n", dev->name, offset, len);
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div_u64_rem(len, spi_flash->page_size, &rem);
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if (rem) {
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printf("%s: len(0x%x) isn't the multiple of page size(0x%x)\n",
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dev->name, len, spi_flash->page_size);
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return -EINVAL;
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}
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div_u64_rem(offset, spi_flash->page_size, &rem);
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if (rem) {
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printf("%s: offset(0x%x) isn't the multiple of page size(0x%x)\n",
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dev->name, offset, spi_flash->page_size);
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return -EINVAL;
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}
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status = spi_claim_bus(spi);
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if (status) {
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debug("dataflash: unable to claim SPI bus\n");
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return status;
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}
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while (len > 0) {
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unsigned int pageaddr;
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int do_block;
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/*
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* Calculate flash page address; use block erase (for speed) if
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* we're at a block boundary and need to erase the whole block.
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*/
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pageaddr = div_u64(offset, spi_flash->page_size);
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do_block = (pageaddr & 0x7) == 0 && len >= blocksize;
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pageaddr = pageaddr << dataflash->page_offset;
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command[0] = do_block ? OP_ERASE_BLOCK : OP_ERASE_PAGE;
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command[1] = (uint8_t)(pageaddr >> 16);
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command[2] = (uint8_t)(pageaddr >> 8);
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command[3] = 0;
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debug("%s ERASE %s: (%x) %x %x %x [%d]\n",
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dev->name, do_block ? "block" : "page",
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command[0], command[1], command[2], command[3],
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pageaddr);
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status = spi_flash_cmd_write(spi, command, 4, NULL, 0);
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if (status < 0) {
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debug("%s: erase send command error!\n", dev->name);
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return -EIO;
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}
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status = dataflash_waitready(spi);
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if (status < 0) {
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debug("%s: erase waitready error!\n", dev->name);
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return status;
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}
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if (do_block) {
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offset += blocksize;
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len -= blocksize;
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} else {
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offset += spi_flash->page_size;
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len -= spi_flash->page_size;
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}
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}
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spi_release_bus(spi);
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return 0;
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}
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/*
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* Read from the DataFlash device.
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* offset : Start offset in flash device
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* len : Amount to read
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* buf : Buffer containing the data
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*/
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static int spi_dataflash_read(struct udevice *dev, u32 offset, size_t len,
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void *buf)
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{
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struct dataflash *dataflash;
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struct spi_flash *spi_flash;
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struct spi_slave *spi;
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unsigned int addr;
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uint8_t *command;
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int status;
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dataflash = dev_get_priv(dev);
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spi_flash = dev_get_uclass_priv(dev);
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spi = spi_flash->spi;
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memset(dataflash->command, 0 , sizeof(dataflash->command));
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command = dataflash->command;
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debug("%s: erase addr=0x%x len 0x%x\n", dev->name, offset, len);
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debug("READ: (%x) %x %x %x\n",
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command[0], command[1], command[2], command[3]);
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/* Calculate flash page/byte address */
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addr = (((unsigned)offset / spi_flash->page_size)
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<< dataflash->page_offset)
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+ ((unsigned)offset % spi_flash->page_size);
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status = spi_claim_bus(spi);
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if (status) {
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debug("dataflash: unable to claim SPI bus\n");
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return status;
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}
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/*
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* Continuous read, max clock = f(car) which may be less than
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* the peak rate available. Some chips support commands with
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* fewer "don't care" bytes. Both buffers stay unchanged.
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*/
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command[0] = OP_READ_CONTINUOUS;
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command[1] = (uint8_t)(addr >> 16);
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command[2] = (uint8_t)(addr >> 8);
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command[3] = (uint8_t)(addr >> 0);
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/* plus 4 "don't care" bytes, command len: 4 + 4 "don't care" bytes */
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status = spi_flash_cmd_read(spi, command, 8, buf, len);
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spi_release_bus(spi);
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return status;
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}
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/*
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* Write to the DataFlash device.
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* offset : Start offset in flash device
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* len : Amount to write
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* buf : Buffer containing the data
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*/
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int spi_dataflash_write(struct udevice *dev, u32 offset, size_t len,
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const void *buf)
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{
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struct dataflash *dataflash;
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struct spi_flash *spi_flash;
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struct spi_slave *spi;
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uint8_t *command;
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unsigned int pageaddr, addr, to, writelen;
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size_t remaining = len;
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u_char *writebuf = (u_char *)buf;
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int status = -EINVAL;
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dataflash = dev_get_priv(dev);
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spi_flash = dev_get_uclass_priv(dev);
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spi = spi_flash->spi;
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memset(dataflash->command, 0 , sizeof(dataflash->command));
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command = dataflash->command;
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debug("%s: write 0x%x..0x%x\n", dev->name, offset, (offset + len));
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pageaddr = ((unsigned)offset / spi_flash->page_size);
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to = ((unsigned)offset % spi_flash->page_size);
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if (to + len > spi_flash->page_size)
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writelen = spi_flash->page_size - to;
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else
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writelen = len;
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status = spi_claim_bus(spi);
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if (status) {
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debug("dataflash: unable to claim SPI bus\n");
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return status;
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}
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while (remaining > 0) {
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debug("write @ %d:%d len=%d\n", pageaddr, to, writelen);
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/*
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* REVISIT:
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* (a) each page in a sector must be rewritten at least
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* once every 10K sibling erase/program operations.
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* (b) for pages that are already erased, we could
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* use WRITE+MWRITE not PROGRAM for ~30% speedup.
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* (c) WRITE to buffer could be done while waiting for
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* a previous MWRITE/MWERASE to complete ...
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* (d) error handling here seems to be mostly missing.
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*
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* Two persistent bits per page, plus a per-sector counter,
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* could support (a) and (b) ... we might consider using
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* the second half of sector zero, which is just one block,
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* to track that state. (On AT91, that sector should also
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* support boot-from-DataFlash.)
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*/
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addr = pageaddr << dataflash->page_offset;
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/* (1) Maybe transfer partial page to Buffer1 */
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if (writelen != spi_flash->page_size) {
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command[0] = OP_TRANSFER_BUF1;
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command[1] = (addr & 0x00FF0000) >> 16;
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command[2] = (addr & 0x0000FF00) >> 8;
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command[3] = 0;
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debug("TRANSFER: (%x) %x %x %x\n",
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command[0], command[1], command[2], command[3]);
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status = spi_flash_cmd_write(spi, command, 4, NULL, 0);
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if (status < 0) {
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debug("%s: write(<pagesize) command error!\n",
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dev->name);
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return -EIO;
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}
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status = dataflash_waitready(spi);
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if (status < 0) {
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debug("%s: write(<pagesize) waitready error!\n",
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dev->name);
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return status;
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}
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}
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/* (2) Program full page via Buffer1 */
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addr += to;
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command[0] = OP_PROGRAM_VIA_BUF1;
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command[1] = (addr & 0x00FF0000) >> 16;
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command[2] = (addr & 0x0000FF00) >> 8;
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command[3] = (addr & 0x000000FF);
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debug("PROGRAM: (%x) %x %x %x\n",
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command[0], command[1], command[2], command[3]);
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status = spi_flash_cmd_write(spi, command,
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4, writebuf, writelen);
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if (status < 0) {
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debug("%s: write send command error!\n", dev->name);
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return -EIO;
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}
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status = dataflash_waitready(spi);
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if (status < 0) {
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debug("%s: write waitready error!\n", dev->name);
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return status;
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}
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#ifdef CONFIG_SPI_DATAFLASH_WRITE_VERIFY
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/* (3) Compare to Buffer1 */
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addr = pageaddr << dataflash->page_offset;
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command[0] = OP_COMPARE_BUF1;
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command[1] = (addr & 0x00FF0000) >> 16;
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command[2] = (addr & 0x0000FF00) >> 8;
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command[3] = 0;
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debug("COMPARE: (%x) %x %x %x\n",
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command[0], command[1], command[2], command[3]);
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status = spi_flash_cmd_write(spi, command,
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4, writebuf, writelen);
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if (status < 0) {
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debug("%s: write(compare) send command error!\n",
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dev->name);
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return -EIO;
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}
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status = dataflash_waitready(spi);
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/* Check result of the compare operation */
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if (status & (1 << 6)) {
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printf("dataflash: write compare page %u, err %d\n",
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pageaddr, status);
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remaining = 0;
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status = -EIO;
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break;
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} else {
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status = 0;
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}
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#endif /* CONFIG_SPI_DATAFLASH_WRITE_VERIFY */
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remaining = remaining - writelen;
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pageaddr++;
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to = 0;
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writebuf += writelen;
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if (remaining > spi_flash->page_size)
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writelen = spi_flash->page_size;
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else
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writelen = remaining;
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}
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spi_release_bus(spi);
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return 0;
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}
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static int add_dataflash(struct udevice *dev, char *name, int nr_pages,
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int pagesize, int pageoffset, char revision)
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{
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struct spi_flash *spi_flash;
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struct dataflash *dataflash;
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dataflash = dev_get_priv(dev);
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spi_flash = dev_get_uclass_priv(dev);
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dataflash->page_offset = pageoffset;
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spi_flash->name = name;
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spi_flash->page_size = pagesize;
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spi_flash->size = nr_pages * pagesize;
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spi_flash->erase_size = pagesize;
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#ifndef CONFIG_SPL_BUILD
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printf("SPI DataFlash: Detected %s with page size ", spi_flash->name);
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print_size(spi_flash->page_size, ", erase size ");
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print_size(spi_flash->erase_size, ", total ");
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print_size(spi_flash->size, "");
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printf(", revision %c", revision);
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puts("\n");
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#endif
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return 0;
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}
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struct flash_info {
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char *name;
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/*
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* JEDEC id has a high byte of zero plus three data bytes:
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* the manufacturer id, then a two byte device id.
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*/
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uint32_t jedec_id;
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/* The size listed here is what works with OP_ERASE_PAGE. */
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unsigned nr_pages;
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uint16_t pagesize;
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uint16_t pageoffset;
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uint16_t flags;
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#define SUP_POW2PS 0x0002 /* supports 2^N byte pages */
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#define IS_POW2PS 0x0001 /* uses 2^N byte pages */
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};
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static struct flash_info dataflash_data[] = {
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/*
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* NOTE: chips with SUP_POW2PS (rev D and up) need two entries,
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* one with IS_POW2PS and the other without. The entry with the
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* non-2^N byte page size can't name exact chip revisions without
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* losing backwards compatibility for cmdlinepart.
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*
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* Those two entries have different name spelling format in order to
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* show their difference obviously.
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* The upper case refer to the chip isn't in normal 2^N bytes page-size
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* mode.
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* The lower case refer to the chip is in normal 2^N bytes page-size
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* mode.
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*
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* These newer chips also support 128-byte security registers (with
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* 64 bytes one-time-programmable) and software write-protection.
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*/
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{ "AT45DB011B", 0x1f2200, 512, 264, 9, SUP_POW2PS},
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{ "at45db011d", 0x1f2200, 512, 256, 8, SUP_POW2PS | IS_POW2PS},
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{ "AT45DB021B", 0x1f2300, 1024, 264, 9, SUP_POW2PS},
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{ "at45db021d", 0x1f2300, 1024, 256, 8, SUP_POW2PS | IS_POW2PS},
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{ "AT45DB041x", 0x1f2400, 2048, 264, 9, SUP_POW2PS},
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{ "at45db041d", 0x1f2400, 2048, 256, 8, SUP_POW2PS | IS_POW2PS},
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{ "AT45DB081B", 0x1f2500, 4096, 264, 9, SUP_POW2PS},
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{ "at45db081d", 0x1f2500, 4096, 256, 8, SUP_POW2PS | IS_POW2PS},
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{ "AT45DB161x", 0x1f2600, 4096, 528, 10, SUP_POW2PS},
|
|
{ "at45db161d", 0x1f2600, 4096, 512, 9, SUP_POW2PS | IS_POW2PS},
|
|
|
|
{ "AT45DB321x", 0x1f2700, 8192, 528, 10, 0}, /* rev C */
|
|
|
|
{ "AT45DB321x", 0x1f2701, 8192, 528, 10, SUP_POW2PS},
|
|
{ "at45db321d", 0x1f2701, 8192, 512, 9, SUP_POW2PS | IS_POW2PS},
|
|
|
|
{ "AT45DB642x", 0x1f2800, 8192, 1056, 11, SUP_POW2PS},
|
|
{ "at45db642d", 0x1f2800, 8192, 1024, 10, SUP_POW2PS | IS_POW2PS},
|
|
};
|
|
|
|
static struct flash_info *jedec_probe(struct spi_slave *spi)
|
|
{
|
|
int tmp;
|
|
uint8_t id[5];
|
|
uint32_t jedec;
|
|
struct flash_info *info;
|
|
int status;
|
|
|
|
/*
|
|
* JEDEC also defines an optional "extended device information"
|
|
* string for after vendor-specific data, after the three bytes
|
|
* we use here. Supporting some chips might require using it.
|
|
*
|
|
* If the vendor ID isn't Atmel's (0x1f), assume this call failed.
|
|
* That's not an error; only rev C and newer chips handle it, and
|
|
* only Atmel sells these chips.
|
|
*/
|
|
tmp = spi_flash_cmd(spi, CMD_READ_ID, id, sizeof(id));
|
|
if (tmp < 0) {
|
|
printf("dataflash: error %d reading JEDEC ID\n", tmp);
|
|
return ERR_PTR(tmp);
|
|
}
|
|
if (id[0] != 0x1f)
|
|
return NULL;
|
|
|
|
jedec = id[0];
|
|
jedec = jedec << 8;
|
|
jedec |= id[1];
|
|
jedec = jedec << 8;
|
|
jedec |= id[2];
|
|
|
|
for (tmp = 0, info = dataflash_data;
|
|
tmp < ARRAY_SIZE(dataflash_data);
|
|
tmp++, info++) {
|
|
if (info->jedec_id == jedec) {
|
|
if (info->flags & SUP_POW2PS) {
|
|
status = dataflash_status(spi);
|
|
if (status < 0) {
|
|
debug("dataflash: status error %d\n",
|
|
status);
|
|
return NULL;
|
|
}
|
|
if (status & 0x1) {
|
|
if (info->flags & IS_POW2PS)
|
|
return info;
|
|
} else {
|
|
if (!(info->flags & IS_POW2PS))
|
|
return info;
|
|
}
|
|
} else {
|
|
return info;
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Treat other chips as errors ... we won't know the right page
|
|
* size (it might be binary) even when we can tell which density
|
|
* class is involved (legacy chip id scheme).
|
|
*/
|
|
printf("dataflash: JEDEC id %06x not handled\n", jedec);
|
|
return ERR_PTR(-ENODEV);
|
|
}
|
|
|
|
/*
|
|
* Detect and initialize DataFlash device, using JEDEC IDs on newer chips
|
|
* or else the ID code embedded in the status bits:
|
|
*
|
|
* Device Density ID code #Pages PageSize Offset
|
|
* AT45DB011B 1Mbit (128K) xx0011xx (0x0c) 512 264 9
|
|
* AT45DB021B 2Mbit (256K) xx0101xx (0x14) 1024 264 9
|
|
* AT45DB041B 4Mbit (512K) xx0111xx (0x1c) 2048 264 9
|
|
* AT45DB081B 8Mbit (1M) xx1001xx (0x24) 4096 264 9
|
|
* AT45DB0161B 16Mbit (2M) xx1011xx (0x2c) 4096 528 10
|
|
* AT45DB0321B 32Mbit (4M) xx1101xx (0x34) 8192 528 10
|
|
* AT45DB0642 64Mbit (8M) xx111xxx (0x3c) 8192 1056 11
|
|
* AT45DB1282 128Mbit (16M) xx0100xx (0x10) 16384 1056 11
|
|
*/
|
|
static int spi_dataflash_probe(struct udevice *dev)
|
|
{
|
|
struct spi_slave *spi = dev_get_parent_priv(dev);
|
|
struct spi_flash *spi_flash;
|
|
struct flash_info *info;
|
|
int status;
|
|
|
|
spi_flash = dev_get_uclass_priv(dev);
|
|
spi_flash->spi = spi;
|
|
spi_flash->dev = dev;
|
|
|
|
status = spi_claim_bus(spi);
|
|
if (status)
|
|
return status;
|
|
|
|
/*
|
|
* Try to detect dataflash by JEDEC ID.
|
|
* If it succeeds we know we have either a C or D part.
|
|
* D will support power of 2 pagesize option.
|
|
* Both support the security register, though with different
|
|
* write procedures.
|
|
*/
|
|
info = jedec_probe(spi);
|
|
if (IS_ERR(info))
|
|
goto err_jedec_probe;
|
|
if (info != NULL) {
|
|
status = add_dataflash(dev, info->name, info->nr_pages,
|
|
info->pagesize, info->pageoffset,
|
|
(info->flags & SUP_POW2PS) ? 'd' : 'c');
|
|
if (status < 0)
|
|
goto err_status;
|
|
}
|
|
|
|
/*
|
|
* Older chips support only legacy commands, identifing
|
|
* capacity using bits in the status byte.
|
|
*/
|
|
status = dataflash_status(spi);
|
|
if (status <= 0 || status == 0xff) {
|
|
printf("dataflash: read status error %d\n", status);
|
|
if (status == 0 || status == 0xff)
|
|
status = -ENODEV;
|
|
goto err_jedec_probe;
|
|
}
|
|
|
|
/*
|
|
* if there's a device there, assume it's dataflash.
|
|
* board setup should have set spi->max_speed_max to
|
|
* match f(car) for continuous reads, mode 0 or 3.
|
|
*/
|
|
switch (status & 0x3c) {
|
|
case 0x0c: /* 0 0 1 1 x x */
|
|
status = add_dataflash(dev, "AT45DB011B", 512, 264, 9, 0);
|
|
break;
|
|
case 0x14: /* 0 1 0 1 x x */
|
|
status = add_dataflash(dev, "AT45DB021B", 1024, 264, 9, 0);
|
|
break;
|
|
case 0x1c: /* 0 1 1 1 x x */
|
|
status = add_dataflash(dev, "AT45DB041x", 2048, 264, 9, 0);
|
|
break;
|
|
case 0x24: /* 1 0 0 1 x x */
|
|
status = add_dataflash(dev, "AT45DB081B", 4096, 264, 9, 0);
|
|
break;
|
|
case 0x2c: /* 1 0 1 1 x x */
|
|
status = add_dataflash(dev, "AT45DB161x", 4096, 528, 10, 0);
|
|
break;
|
|
case 0x34: /* 1 1 0 1 x x */
|
|
status = add_dataflash(dev, "AT45DB321x", 8192, 528, 10, 0);
|
|
break;
|
|
case 0x38: /* 1 1 1 x x x */
|
|
case 0x3c:
|
|
status = add_dataflash(dev, "AT45DB642x", 8192, 1056, 11, 0);
|
|
break;
|
|
/* obsolete AT45DB1282 not (yet?) supported */
|
|
default:
|
|
printf("dataflash: unsupported device (%x)\n", status & 0x3c);
|
|
status = -ENODEV;
|
|
goto err_status;
|
|
}
|
|
|
|
return status;
|
|
|
|
err_status:
|
|
spi_free_slave(spi);
|
|
err_jedec_probe:
|
|
spi_release_bus(spi);
|
|
return status;
|
|
}
|
|
|
|
static const struct dm_spi_flash_ops spi_dataflash_ops = {
|
|
.read = spi_dataflash_read,
|
|
.write = spi_dataflash_write,
|
|
.erase = spi_dataflash_erase,
|
|
};
|
|
|
|
static const struct udevice_id spi_dataflash_ids[] = {
|
|
{ .compatible = "atmel,at45", },
|
|
{ .compatible = "atmel,dataflash", },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(spi_dataflash) = {
|
|
.name = "spi_dataflash",
|
|
.id = UCLASS_SPI_FLASH,
|
|
.of_match = spi_dataflash_ids,
|
|
.probe = spi_dataflash_probe,
|
|
.priv_auto_alloc_size = sizeof(struct dataflash),
|
|
.ops = &spi_dataflash_ops,
|
|
};
|