mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-12 07:57:21 +00:00
77b11f7604
As part of the effort of making U-Boot work with the same device tree as Linux, there is an issue with the "xfi" phy-mode. To be precise, in Linux there was a discussion (for those who have time to read: https://lore.kernel.org/netdev/1576768881-24971-2-git-send-email-madalin.bucur@oss.nxp.com/) which led to a patch: https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=c114574ebfdf42f826776f717c8056a00fa94881 TL;DR: "xfi" was standardized in Linux as "10gbase-r". This patch changes the relevant occurrences in U-Boot to use "10gbase-r" instead of "xfi" wherever applicable. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
54 lines
1.9 KiB
Text
54 lines
1.9 KiB
Text
Overview
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--------
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The LS1043A Reference Design Board (RDB) is a high-performance computing,
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evaluation, and development platform that supports the QorIQ LS1043A
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LayerScape Architecture processor. The LS1043ARDB provides SW development
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platform for the Freescale LS1043A processor series, with a complete
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debugging environment. The LS1043A RDB is lead-free and RoHS-compliant.
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LS1043A SoC Overview
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--------------------
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Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A
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SoC overview.
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LS1043ARDB board Overview
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-----------------------
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- SERDES Connections, 4 lanes supporting:
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- PCI Express 2.0 with two PCIe connectors supporting: miniPCIe card and
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standard PCIe card
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- QSGMII with x4 RJ45 connector
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- 10GBase-R with x1 RJ45 connector
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- DDR Controller
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- 2GB 32bits DDR4 SDRAM. Support rates of up to 1600MT/s
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-IFC/Local Bus
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- One 128MB NOR flash 16-bit data bus
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- One 512 MB NAND flash with ECC support
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- CPLD connection
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- USB 3.0
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- Two super speed USB 3.0 Type A ports
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- SDHC: connects directly to a full SD/MMC slot
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- DSPI: 16 MB high-speed flash Memory for boot code and storage (up to 108MHz)
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- 4 I2C controllers
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- UART
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- Two 4-pin serial ports at up to 115.2 Kbit/s
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- Two DB9 D-Type connectors supporting one Serial port each
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- ARM JTAG support
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Memory map from core's view
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----------------------------
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Start Address End Address Description Size
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0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB
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0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB
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0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB
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0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB
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0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB
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0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB
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0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB
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0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB
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0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB
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Booting Options
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---------------
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a) NOR boot
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b) NAND boot
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c) SD boot
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