mirror of
https://github.com/AsahiLinux/u-boot
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b799eabc7e
Create a do-nothing driver for each sunxi pin controller variant. Since only one driver can automatically bind to a DT node, since the GPIO driver already requires a manual binding process, and since the pinctrl driver needs access to some of the same information, refactor the GPIO driver to be bound by the pinctrl driver. This commit should cause no functional change. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
227 lines
4.7 KiB
C
227 lines
4.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
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*
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* Based on earlier arch/arm/cpu/armv7/sunxi/gpio.c:
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*
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* (C) Copyright 2007-2011
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <dt-bindings/gpio/gpio.h>
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#if !CONFIG_IS_ENABLED(DM_GPIO)
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static int sunxi_gpio_output(u32 pin, u32 val)
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{
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u32 dat;
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u32 bank = GPIO_BANK(pin);
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u32 num = GPIO_NUM(pin);
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struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
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dat = readl(&pio->dat);
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if (val)
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dat |= 0x1 << num;
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else
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dat &= ~(0x1 << num);
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writel(dat, &pio->dat);
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return 0;
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}
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static int sunxi_gpio_input(u32 pin)
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{
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u32 dat;
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u32 bank = GPIO_BANK(pin);
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u32 num = GPIO_NUM(pin);
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struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
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dat = readl(&pio->dat);
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dat >>= num;
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return dat & 0x1;
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}
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int gpio_request(unsigned gpio, const char *label)
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{
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return 0;
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}
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int gpio_free(unsigned gpio)
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{
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return 0;
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}
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int gpio_direction_input(unsigned gpio)
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{
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sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_INPUT);
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return 0;
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}
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int gpio_direction_output(unsigned gpio, int value)
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{
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sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_OUTPUT);
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return sunxi_gpio_output(gpio, value);
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}
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int gpio_get_value(unsigned gpio)
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{
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return sunxi_gpio_input(gpio);
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}
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int gpio_set_value(unsigned gpio, int value)
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{
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return sunxi_gpio_output(gpio, value);
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}
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int sunxi_name_to_gpio(const char *name)
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{
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int group = 0;
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int groupsize = 9 * 32;
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long pin;
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char *eptr;
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if (*name == 'P' || *name == 'p')
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name++;
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if (*name >= 'A') {
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group = *name - (*name > 'a' ? 'a' : 'A');
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groupsize = 32;
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name++;
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}
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pin = simple_strtol(name, &eptr, 10);
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if (!*name || *eptr)
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return -1;
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if (pin < 0 || pin > groupsize || group >= 9)
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return -1;
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return group * 32 + pin;
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}
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#endif /* DM_GPIO */
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#if CONFIG_IS_ENABLED(DM_GPIO)
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/* TODO(sjg@chromium.org): Remove this function and use device tree */
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int sunxi_name_to_gpio(const char *name)
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{
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unsigned int gpio;
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int ret;
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#if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO
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char lookup[8];
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if (strcasecmp(name, "AXP0-VBUS-DETECT") == 0) {
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sprintf(lookup, SUNXI_GPIO_AXP0_PREFIX "%d",
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SUNXI_GPIO_AXP0_VBUS_DETECT);
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name = lookup;
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} else if (strcasecmp(name, "AXP0-VBUS-ENABLE") == 0) {
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sprintf(lookup, SUNXI_GPIO_AXP0_PREFIX "%d",
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SUNXI_GPIO_AXP0_VBUS_ENABLE);
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name = lookup;
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}
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#endif
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ret = gpio_lookup_name(name, NULL, NULL, &gpio);
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return ret ? ret : gpio;
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}
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static int sunxi_gpio_get_value(struct udevice *dev, unsigned offset)
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{
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struct sunxi_gpio_plat *plat = dev_get_plat(dev);
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u32 num = GPIO_NUM(offset);
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unsigned dat;
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dat = readl(&plat->regs->dat);
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dat >>= num;
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return dat & 0x1;
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}
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static int sunxi_gpio_get_function(struct udevice *dev, unsigned offset)
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{
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struct sunxi_gpio_plat *plat = dev_get_plat(dev);
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int func;
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func = sunxi_gpio_get_cfgbank(plat->regs, offset);
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if (func == SUNXI_GPIO_OUTPUT)
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return GPIOF_OUTPUT;
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else if (func == SUNXI_GPIO_INPUT)
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return GPIOF_INPUT;
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else
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return GPIOF_FUNC;
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}
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static int sunxi_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
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struct ofnode_phandle_args *args)
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{
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int ret;
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ret = device_get_child(dev, args->args[0], &desc->dev);
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if (ret)
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return ret;
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desc->offset = args->args[1];
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desc->flags = gpio_flags_xlate(args->args[2]);
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return 0;
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}
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static int sunxi_gpio_set_flags(struct udevice *dev, unsigned int offset,
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ulong flags)
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{
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struct sunxi_gpio_plat *plat = dev_get_plat(dev);
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if (flags & GPIOD_IS_OUT) {
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u32 value = !!(flags & GPIOD_IS_OUT_ACTIVE);
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u32 num = GPIO_NUM(offset);
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clrsetbits_le32(&plat->regs->dat, 1 << num, value << num);
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sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_OUTPUT);
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} else if (flags & GPIOD_IS_IN) {
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u32 pull = 0;
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if (flags & GPIOD_PULL_UP)
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pull = 1;
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else if (flags & GPIOD_PULL_DOWN)
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pull = 2;
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sunxi_gpio_set_pull_bank(plat->regs, offset, pull);
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sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_INPUT);
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}
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return 0;
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}
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static const struct dm_gpio_ops gpio_sunxi_ops = {
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.get_value = sunxi_gpio_get_value,
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.get_function = sunxi_gpio_get_function,
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.xlate = sunxi_gpio_xlate,
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.set_flags = sunxi_gpio_set_flags,
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};
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static int gpio_sunxi_probe(struct udevice *dev)
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{
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struct sunxi_gpio_plat *plat = dev_get_plat(dev);
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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/* Tell the uclass how many GPIOs we have */
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if (plat) {
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uc_priv->gpio_count = SUNXI_GPIOS_PER_BANK;
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uc_priv->bank_name = plat->bank_name;
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}
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return 0;
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}
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U_BOOT_DRIVER(gpio_sunxi) = {
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.name = "gpio_sunxi",
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.id = UCLASS_GPIO,
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.probe = gpio_sunxi_probe,
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.ops = &gpio_sunxi_ops,
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};
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#endif /* DM_GPIO */
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