u-boot/cpu/blackfin/cache.S
Mike Frysinger 05b75e4883 Blackfin: fix dcache handling when doing dma memcpy's
Our dcache invalidate function doesn't just invalidate, it also flushes.
So rename the function accordingly and fix the dma_memcpy() function so it
doesn't inadvertently corrupt the data destination.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-01-28 13:26:12 -05:00

61 lines
1 KiB
ArmAsm

/* cache.S - low level cache handling routines
* Copyright (C) 2003-2007 Analog Devices Inc.
* Licensed under the GPL-2 or later.
*/
#include <asm/linkage.h>
#include <config.h>
#include <asm/blackfin.h>
.text
.align 2
ENTRY(_blackfin_icache_flush_range)
R2 = -32;
R2 = R0 & R2;
P0 = R2;
P1 = R1;
CSYNC;
1:
IFLUSH[P0++];
CC = P0 < P1(iu);
IF CC JUMP 1b(bp);
IFLUSH[P0];
SSYNC;
RTS;
ENDPROC(_blackfin_icache_flush_range)
ENTRY(_blackfin_dcache_flush_range)
R2 = -32;
R2 = R0 & R2;
P0 = R2;
P1 = R1;
CSYNC;
1:
FLUSH[P0++];
CC = P0 < P1(iu);
IF CC JUMP 1b(bp);
FLUSH[P0];
SSYNC;
RTS;
ENDPROC(_blackfin_dcache_flush_range)
ENTRY(_blackfin_dcache_flush_invalidate_range)
R2 = -32;
R2 = R0 & R2;
P0 = R2;
P1 = R1;
CSYNC;
1:
FLUSHINV[P0++];
CC = P0 < P1(iu);
IF CC JUMP 1b(bp);
/*
* If the data crosses a cache line, then we'll be pointing to
* the last cache line, but won't have flushed/invalidated it yet, so do
* one more.
*/
FLUSHINV[P0];
SSYNC;
RTS;
ENDPROC(_blackfin_dcache_flush_invalidate_range)