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93e1459641
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Drop changes for PEP 4 following python tools] Signed-off-by: Tom Rini <trini@ti.com>
145 lines
3.9 KiB
C
145 lines
3.9 KiB
C
/*
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* (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
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* (C) Copyright 2011, Julius Baxter <julius@opencores.org>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/system.h>
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#include <asm/openrisc_exc.h>
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static volatile int illegal_instruction;
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static void illegal_instruction_handler(void)
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{
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ulong *epcr = (ulong *)mfspr(SPR_EPCR_BASE);
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/* skip over the illegal instruction */
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mtspr(SPR_EPCR_BASE, (ulong)(++epcr));
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illegal_instruction = 1;
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}
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static void checkinstructions(void)
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{
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ulong ra = 1, rb = 1, rc;
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exception_install_handler(EXC_ILLEGAL_INSTR,
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illegal_instruction_handler);
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illegal_instruction = 0;
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asm volatile("l.mul %0,%1,%2" : "=r" (rc) : "r" (ra), "r" (rb));
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printf(" Hardware multiplier: %s\n",
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illegal_instruction ? "no" : "yes");
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illegal_instruction = 0;
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asm volatile("l.div %0,%1,%2" : "=r" (rc) : "r" (ra), "r" (rb));
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printf(" Hardware divider: %s\n",
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illegal_instruction ? "no" : "yes");
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exception_free_handler(EXC_ILLEGAL_INSTR);
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}
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int checkcpu(void)
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{
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ulong upr = mfspr(SPR_UPR);
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ulong vr = mfspr(SPR_VR);
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ulong iccfgr = mfspr(SPR_ICCFGR);
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ulong dccfgr = mfspr(SPR_DCCFGR);
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ulong immucfgr = mfspr(SPR_IMMUCFGR);
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ulong dmmucfgr = mfspr(SPR_DMMUCFGR);
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ulong cpucfgr = mfspr(SPR_CPUCFGR);
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uint ver = (vr & SPR_VR_VER) >> 24;
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uint rev = vr & SPR_VR_REV;
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uint block_size;
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uint ways;
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uint sets;
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printf("CPU: OpenRISC-%x00 (rev %d) @ %d MHz\n",
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ver, rev, (CONFIG_SYS_CLK_FREQ / 1000000));
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if (upr & SPR_UPR_DCP) {
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block_size = (dccfgr & SPR_DCCFGR_CBS) ? 32 : 16;
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ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
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printf(" D-Cache: %d bytes, %d bytes/line, %d way(s)\n",
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checkdcache(), block_size, ways);
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} else {
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printf(" D-Cache: no\n");
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}
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if (upr & SPR_UPR_ICP) {
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block_size = (iccfgr & SPR_ICCFGR_CBS) ? 32 : 16;
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ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
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printf(" I-Cache: %d bytes, %d bytes/line, %d way(s)\n",
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checkicache(), block_size, ways);
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} else {
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printf(" I-Cache: no\n");
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}
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if (upr & SPR_UPR_DMP) {
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sets = 1 << ((dmmucfgr & SPR_DMMUCFGR_NTS) >> 2);
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ways = (dmmucfgr & SPR_DMMUCFGR_NTW) + 1;
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printf(" DMMU: %d sets, %d way(s)\n",
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sets, ways);
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} else {
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printf(" DMMU: no\n");
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}
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if (upr & SPR_UPR_IMP) {
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sets = 1 << ((immucfgr & SPR_IMMUCFGR_NTS) >> 2);
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ways = (immucfgr & SPR_IMMUCFGR_NTW) + 1;
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printf(" IMMU: %d sets, %d way(s)\n",
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sets, ways);
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} else {
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printf(" IMMU: no\n");
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}
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printf(" MAC unit: %s\n",
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(upr & SPR_UPR_MP) ? "yes" : "no");
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printf(" Debug unit: %s\n",
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(upr & SPR_UPR_DUP) ? "yes" : "no");
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printf(" Performance counters: %s\n",
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(upr & SPR_UPR_PCUP) ? "yes" : "no");
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printf(" Power management: %s\n",
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(upr & SPR_UPR_PMP) ? "yes" : "no");
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printf(" Interrupt controller: %s\n",
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(upr & SPR_UPR_PICP) ? "yes" : "no");
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printf(" Timer: %s\n",
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(upr & SPR_UPR_TTP) ? "yes" : "no");
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printf(" Custom unit(s): %s\n",
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(upr & SPR_UPR_CUP) ? "yes" : "no");
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printf(" Supported instructions:\n");
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printf(" ORBIS32: %s\n",
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(cpucfgr & SPR_CPUCFGR_OB32S) ? "yes" : "no");
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printf(" ORBIS64: %s\n",
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(cpucfgr & SPR_CPUCFGR_OB64S) ? "yes" : "no");
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printf(" ORFPX32: %s\n",
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(cpucfgr & SPR_CPUCFGR_OF32S) ? "yes" : "no");
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printf(" ORFPX64: %s\n",
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(cpucfgr & SPR_CPUCFGR_OF64S) ? "yes" : "no");
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checkinstructions();
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return 0;
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}
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int cleanup_before_linux(void)
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{
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disable_interrupts();
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return 0;
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}
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extern void __reset(void);
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int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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disable_interrupts();
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/* Code the jump to __reset here as the compiler is prone to
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emitting a bad jump instruction if the function is in flash */
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__asm__("l.movhi r1,hi(__reset); \
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l.ori r1,r1,lo(__reset); \
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l.jr r1");
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/* not reached, __reset does not return */
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return 0;
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}
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