u-boot/drivers/ram/rockchip/sdram-px30-ddr3-detect-333.inc
YouMin Chen 39edfaa758 ram: px30: add sdram driver
Add the sdram driver for PX30 to support ddr3, ddr4, lpddr2 and lpddr3.

For TPL_BUILD, the driver implement full dram init and without DM
support due to the limit of internal SRAM size.
For SPL and U-Boot proper, it's a simple driver with dm for get
dram_info like other SoCs.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00

72 lines
1.7 KiB
PHP

{
{
{
.rank = 0x1,
.col = 0xC,
.bk = 0x3,
.bw = 0x1,
.dbw = 0x0,
.row_3_4 = 0x0,
.cs0_row = 0x10,
.cs1_row = 0x10,
.cs0_high16bit_row = 0x10,
.cs1_high16bit_row = 0x10,
.ddrconfig = 0,
},
{
{0x290b0609},
{0x08020401},
{0x00000002},
{0x00001111},
{0x0000000c},
{0x00000222},
0x000000ff
}
},
{
.ddr_freq = 333,
.dramtype = DDR3,
.num_channels = 1,
.stride = 0,
.odt = 0,
},
{
{
{0x00000000, 0x43041001}, /* MSTR */
{0x00000064, 0x0028003b}, /* RFSHTMG */
{0x000000d0, 0x00020053}, /* INIT0 */
{0x000000d4, 0x00020000}, /* INIT1 */
{0x000000d8, 0x00000100}, /* INIT2 */
{0x000000dc, 0x03200000}, /* INIT3 */
{0x000000e0, 0x00000000}, /* INIT4 */
{0x000000e4, 0x00090000}, /* INIT5 */
{0x000000f4, 0x000f012f}, /* RANKCTL */
{0x00000100, 0x07090b06}, /* DRAMTMG0 */
{0x00000104, 0x00050209}, /* DRAMTMG1 */
{0x00000108, 0x03030407}, /* DRAMTMG2 */
{0x0000010c, 0x00202006}, /* DRAMTMG3 */
{0x00000110, 0x03020204}, /* DRAMTMG4 */
{0x00000114, 0x03030202}, /* DRAMTMG5 */
{0x00000120, 0x00000903}, /* DRAMTMG8 */
{0x00000180, 0x00800020}, /* ZQCTL0 */
{0x00000184, 0x00000000}, /* ZQCTL1 */
{0x00000190, 0x07010001}, /* DFITMG0 */
{0x00000198, 0x07000101}, /* DFILPCFG0 */
{0x000001a0, 0xc0400003}, /* DFIUPD0 */
{0x00000240, 0x06000604}, /* ODTCFG */
{0x00000244, 0x00000201}, /* ODTMAP */
{0x00000250, 0x00001f00}, /* SCHED */
{0x00000490, 0x00000001}, /* PCTRL_0 */
{0xffffffff, 0xffffffff}
}
},
{
{
{0x00000004, 0x0000000a}, /* PHYREG01 */
{0x00000028, 0x00000006}, /* PHYREG0A */
{0x0000002c, 0x00000000}, /* PHYREG0B */
{0x00000030, 0x00000005}, /* PHYREG0C */
{0xffffffff, 0xffffffff}
}
}
},