mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-13 14:53:06 +00:00
382b837134
To determine whether we have been booted from an eMMC boot partition, we replay some of the checks that the BROM must have done to successfully load the SPL. This involves a checksum check, which currently relies on the SPL being wrapped in an "eGON" header. If a board has secure boot enabled, the BROM will only accept the "TOC0" format, which is internally very different, but uses the same checksumming algorithm. Actually the only difference for calculating the checksum is that the size of the SPL is stored at a different offset. Do a header check to determine whether we deal with an eGON or TOC0 format, then set the SPL size accordingly. The rest of the code is unchanged. This fixes booting from an eMMC boot partition on devices with secure boot enabled, like the Remix Mini PC. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org>
507 lines
16 KiB
C
507 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
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*
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* (C) Copyright 2007-2011
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*
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* Some init for sunxi platform.
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <init.h>
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#include <log.h>
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#include <mmc.h>
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#include <i2c.h>
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#include <serial.h>
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#include <spl.h>
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#include <asm/cache.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/spl.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/timer.h>
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#include <asm/arch/tzpc.h>
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#include <asm/arch/mmc.h>
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#include <linux/compiler.h>
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struct fel_stash {
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uint32_t sp;
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uint32_t lr;
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uint32_t cpsr;
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uint32_t sctlr;
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uint32_t vbar;
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};
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struct fel_stash fel_stash __section(".data");
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#ifdef CONFIG_ARM64
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#include <asm/armv8/mmu.h>
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static struct mm_region sunxi_mem_map[] = {
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{
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/* SRAM, MMIO regions */
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0x40000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE
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}, {
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/* RAM */
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.virt = 0x40000000UL,
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.phys = 0x40000000UL,
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.size = CONFIG_SUNXI_DRAM_MAX_SIZE,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = sunxi_mem_map;
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phys_size_t board_get_usable_ram_top(phys_size_t total_size)
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{
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/* Some devices (like the EMAC) have a 32-bit DMA limit. */
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if (gd->ram_top > (1ULL << 32))
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return 1ULL << 32;
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return gd->ram_top;
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}
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#endif /* CONFIG_ARM64 */
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#ifdef CONFIG_SPL_BUILD
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static int gpio_init(void)
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{
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__maybe_unused uint val;
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#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
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#if defined(CONFIG_MACH_SUN4I) || \
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defined(CONFIG_MACH_SUN7I) || \
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defined(CONFIG_MACH_SUN8I_R40)
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/* disable GPB22,23 as uart0 tx,rx to avoid conflict */
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sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
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sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
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#endif
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#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || \
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defined(CONFIG_MACH_SUN7I) || defined(CONFIG_MACH_SUN8I_R40) || \
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defined(CONFIG_MACH_SUN9I)
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sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
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sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
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#else
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sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
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sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
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#endif
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sunxi_gpio_set_pull(SUNXI_GPF(4), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNIV)
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sunxi_gpio_set_cfgpin(SUNXI_GPE(0), SUNIV_GPE_UART0);
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sunxi_gpio_set_cfgpin(SUNXI_GPE(1), SUNIV_GPE_UART0);
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sunxi_gpio_set_pull(SUNXI_GPE(1), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \
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defined(CONFIG_MACH_SUN7I) || \
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defined(CONFIG_MACH_SUN8I_R40))
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sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
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sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
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sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
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sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
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sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
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sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
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sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
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sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
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sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
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sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
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sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
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sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNXI_H3_H5)
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sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
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sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
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sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I)
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sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0);
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sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0);
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sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H6)
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sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H6_GPH_UART0);
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sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H6_GPH_UART0);
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sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H616)
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sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H616_GPH_UART0);
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sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H616_GPH_UART0);
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sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
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sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
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sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
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sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S)
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sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0);
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sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0);
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sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
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sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
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sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
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sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUNIV)
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sunxi_gpio_set_cfgpin(SUNXI_GPA(2), SUNIV_GPE_UART0);
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sunxi_gpio_set_cfgpin(SUNXI_GPA(3), SUNIV_GPE_UART0);
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sunxi_gpio_set_pull(SUNXI_GPA(3), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
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sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
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sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
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sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I_H3)
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sunxi_gpio_set_cfgpin(SUNXI_GPA(0), SUN8I_H3_GPA_UART2);
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sunxi_gpio_set_cfgpin(SUNXI_GPA(1), SUN8I_H3_GPA_UART2);
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sunxi_gpio_set_pull(SUNXI_GPA(1), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
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sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
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sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
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sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
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sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
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sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
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sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
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#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN8I) && \
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!defined(CONFIG_MACH_SUN8I_R40)
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sunxi_gpio_set_cfgpin(SUNXI_GPG(6), SUN8I_GPG_UART1);
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sunxi_gpio_set_cfgpin(SUNXI_GPG(7), SUN8I_GPG_UART1);
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sunxi_gpio_set_pull(SUNXI_GPG(7), SUNXI_GPIO_PULL_UP);
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#else
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#error Unsupported console port number. Please fix pin mux settings in board.c
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#endif
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#ifdef CONFIG_SUN50I_GEN_H6
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/* Update PIO power bias configuration by copy hardware detected value */
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val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
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writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
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val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
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writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
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#endif
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return 0;
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}
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static int spl_board_load_image(struct spl_image_info *spl_image,
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struct spl_boot_device *bootdev)
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{
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debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
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return_to_fel(fel_stash.sp, fel_stash.lr);
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return 0;
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}
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SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
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#endif /* CONFIG_SPL_BUILD */
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#define SUNXI_INVALID_BOOT_SOURCE -1
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static int suniv_get_boot_source(void)
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{
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/* Get the last function call from BootROM's stack. */
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u32 brom_call = *(u32 *)(uintptr_t)(fel_stash.sp - 4);
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/* translate SUNIV BootROM stack to standard SUNXI boot sources */
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switch (brom_call) {
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case SUNIV_BOOTED_FROM_MMC0:
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return SUNXI_BOOTED_FROM_MMC0;
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case SUNIV_BOOTED_FROM_SPI:
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return SUNXI_BOOTED_FROM_SPI;
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case SUNIV_BOOTED_FROM_MMC1:
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return SUNXI_BOOTED_FROM_MMC2;
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/* SPI NAND is not supported yet. */
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case SUNIV_BOOTED_FROM_NAND:
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return SUNXI_INVALID_BOOT_SOURCE;
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}
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/* If we get here something went wrong try to boot from FEL.*/
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printf("Unknown boot source from BROM: 0x%x\n", brom_call);
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return SUNXI_INVALID_BOOT_SOURCE;
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}
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static int sunxi_egon_valid(struct boot_file_head *egon_head)
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{
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return !memcmp(egon_head->magic, BOOT0_MAGIC, 8); /* eGON.BT0 */
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}
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static int sunxi_toc0_valid(struct toc0_main_info *toc0_info)
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{
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return !memcmp(toc0_info->name, TOC0_MAIN_INFO_NAME, 8); /* TOC0.GLH */
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}
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static int sunxi_get_boot_source(void)
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{
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struct boot_file_head *egon_head = (void *)SPL_ADDR;
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struct toc0_main_info *toc0_info = (void *)SPL_ADDR;
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/*
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* On the ARMv5 SoCs, the SPL header in SRAM is overwritten by the
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* exception vectors in U-Boot proper, so we won't find any
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* information there. Also the FEL stash is only valid in the SPL,
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* so we can't use that either. So if this is called from U-Boot
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* proper, just return MMC0 as a placeholder, for now.
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*/
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if (IS_ENABLED(CONFIG_MACH_SUNIV) &&
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!IS_ENABLED(CONFIG_SPL_BUILD))
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return SUNXI_BOOTED_FROM_MMC0;
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if (IS_ENABLED(CONFIG_MACH_SUNIV))
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return suniv_get_boot_source();
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if (sunxi_egon_valid(egon_head))
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return readb(&egon_head->boot_media);
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if (sunxi_toc0_valid(toc0_info))
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return readb(&toc0_info->platform[0]);
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/* Not a valid image, so we must have been booted via FEL. */
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return SUNXI_INVALID_BOOT_SOURCE;
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}
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/* The sunxi internal brom will try to loader external bootloader
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* from mmc0, nand flash, mmc2.
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*/
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uint32_t sunxi_get_boot_device(void)
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{
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int boot_source = sunxi_get_boot_source();
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/*
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* When booting from the SD card or NAND memory, the "eGON.BT0"
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* signature is expected to be found in memory at the address 0x0004
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* (see the "mksunxiboot" tool, which generates this header).
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*
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* When booting in the FEL mode over USB, this signature is patched in
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* memory and replaced with something else by the 'fel' tool. This other
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* signature is selected in such a way, that it can't be present in a
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* valid bootable SD card image (because the BROM would refuse to
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* execute the SPL in this case).
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*
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* This checks for the signature and if it is not found returns to
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* the FEL code in the BROM to wait and receive the main u-boot
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* binary over USB. If it is found, it determines where SPL was
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* read from.
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*/
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switch (boot_source) {
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case SUNXI_INVALID_BOOT_SOURCE:
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return BOOT_DEVICE_BOARD;
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case SUNXI_BOOTED_FROM_MMC0:
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case SUNXI_BOOTED_FROM_MMC0_HIGH:
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return BOOT_DEVICE_MMC1;
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case SUNXI_BOOTED_FROM_NAND:
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return BOOT_DEVICE_NAND;
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case SUNXI_BOOTED_FROM_MMC2:
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case SUNXI_BOOTED_FROM_MMC2_HIGH:
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return BOOT_DEVICE_MMC2;
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case SUNXI_BOOTED_FROM_SPI:
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return BOOT_DEVICE_SPI;
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}
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panic("Unknown boot source %d\n", boot_source);
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return -1; /* Never reached */
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}
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#ifdef CONFIG_SPL_BUILD
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uint32_t sunxi_get_spl_size(void)
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{
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struct boot_file_head *egon_head = (void *)SPL_ADDR;
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struct toc0_main_info *toc0_info = (void *)SPL_ADDR;
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if (sunxi_egon_valid(egon_head))
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return readl(&egon_head->length);
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if (sunxi_toc0_valid(toc0_info))
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return readl(&toc0_info->length);
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/* Not a valid image, so use the default U-Boot offset. */
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return 0;
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}
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/*
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* The eGON SPL image can be located at 8KB or at 128KB into an SD card or
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* an eMMC device. The boot source has bit 4 set in the latter case.
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* By adding 120KB to the normal offset when booting from a "high" location
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* we can support both cases.
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* Also U-Boot proper is located at least 32KB after the SPL, but will
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* immediately follow the SPL if that is bigger than that.
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*/
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unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
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unsigned long raw_sect)
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{
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unsigned long spl_size = sunxi_get_spl_size();
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unsigned long sector;
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sector = max(raw_sect, spl_size / 512);
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switch (sunxi_get_boot_source()) {
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case SUNXI_BOOTED_FROM_MMC0_HIGH:
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case SUNXI_BOOTED_FROM_MMC2_HIGH:
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sector += (128 - 8) * 2;
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break;
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}
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return sector;
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}
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u32 spl_boot_device(void)
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{
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return sunxi_get_boot_device();
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}
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__weak void sunxi_sram_init(void)
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{
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}
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/*
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* When booting from an eMMC boot partition, the SPL puts the same boot
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* source code into SRAM A1 as when loading the SPL from the normal
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* eMMC user data partition: 0x2. So to know where we have been loaded
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* from, we repeat the BROM algorithm here: checking for a valid eGON boot
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* image at offset 0 of a (potentially) selected boot partition.
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* If any of the conditions is not met, it must have been the eMMC user
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* data partition.
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*/
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static bool sunxi_valid_emmc_boot(struct mmc *mmc)
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{
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struct blk_desc *bd = mmc_get_blk_desc(mmc);
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u32 *buffer = (void *)(uintptr_t)CONFIG_TEXT_BASE;
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struct boot_file_head *egon_head = (void *)buffer;
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struct toc0_main_info *toc0_info = (void *)buffer;
|
|
int bootpart = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
|
|
uint32_t spl_size, emmc_checksum, chksum = 0;
|
|
ulong count;
|
|
|
|
/* The BROM requires BOOT_ACK to be enabled. */
|
|
if (!EXT_CSD_EXTRACT_BOOT_ACK(mmc->part_config))
|
|
return false;
|
|
|
|
/*
|
|
* The BOOT_BUS_CONDITION register must be 4-bit SDR, with (0x09)
|
|
* or without (0x01) high speed timings.
|
|
*/
|
|
if ((mmc->ext_csd[EXT_CSD_BOOT_BUS_WIDTH] & 0x1b) != 0x01 &&
|
|
(mmc->ext_csd[EXT_CSD_BOOT_BUS_WIDTH] & 0x1b) != 0x09)
|
|
return false;
|
|
|
|
/* Partition 0 is the user data partition, bootpart must be 1 or 2. */
|
|
if (bootpart != 1 && bootpart != 2)
|
|
return false;
|
|
|
|
/* Failure to switch to the boot partition is fatal. */
|
|
if (mmc_switch_part(mmc, bootpart))
|
|
return false;
|
|
|
|
/* Read the first block to do some sanity checks on the eGON header. */
|
|
count = blk_dread(bd, 0, 1, buffer);
|
|
if (count != 1)
|
|
return false;
|
|
|
|
if (sunxi_egon_valid(egon_head))
|
|
spl_size = egon_head->length;
|
|
else if (sunxi_toc0_valid(toc0_info))
|
|
spl_size = toc0_info->length;
|
|
else
|
|
return false;
|
|
|
|
/* Read the rest of the SPL now we know it's halfway sane. */
|
|
count = blk_dread(bd, 1, DIV_ROUND_UP(spl_size, bd->blksz) - 1,
|
|
buffer + bd->blksz / 4);
|
|
|
|
/* Save the checksum and replace it with the "stamp value". */
|
|
emmc_checksum = buffer[3];
|
|
buffer[3] = 0x5f0a6c39;
|
|
|
|
/* The checksum is a simple ignore-carry addition of all words. */
|
|
for (count = 0; count < spl_size / 4; count++)
|
|
chksum += buffer[count];
|
|
|
|
debug("eMMC boot part SPL checksum: stored: 0x%08x, computed: 0x%08x\n",
|
|
emmc_checksum, chksum);
|
|
|
|
return emmc_checksum == chksum;
|
|
}
|
|
|
|
u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
|
|
{
|
|
static u32 result = ~0;
|
|
|
|
if (result != ~0)
|
|
return result;
|
|
|
|
result = MMCSD_MODE_RAW;
|
|
if (!IS_SD(mmc) && IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT)) {
|
|
if (sunxi_valid_emmc_boot(mmc))
|
|
result = MMCSD_MODE_EMMCBOOT;
|
|
else
|
|
mmc_switch_part(mmc, 0);
|
|
}
|
|
|
|
debug("%s(): %s part\n", __func__,
|
|
result == MMCSD_MODE_RAW ? "user" : "boot");
|
|
|
|
return result;
|
|
}
|
|
|
|
void board_init_f(ulong dummy)
|
|
{
|
|
sunxi_sram_init();
|
|
|
|
#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
|
|
/* Enable non-secure access to some peripherals */
|
|
tzpc_init();
|
|
#endif
|
|
|
|
clock_init();
|
|
timer_init();
|
|
gpio_init();
|
|
|
|
spl_init();
|
|
preloader_console_init();
|
|
|
|
#if CONFIG_IS_ENABLED(I2C) && CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
|
|
/* Needed early by sunxi_board_init if PMU is enabled */
|
|
i2c_init_board();
|
|
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
|
|
#endif
|
|
sunxi_board_init();
|
|
}
|
|
#endif /* CONFIG_SPL_BUILD */
|
|
|
|
#if !CONFIG_IS_ENABLED(SYSRESET)
|
|
void reset_cpu(void)
|
|
{
|
|
#if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40)
|
|
static const struct sunxi_wdog *wdog =
|
|
&((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
|
|
|
|
/* Set the watchdog for its shortest interval (.5s) and wait */
|
|
writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
|
|
writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
|
|
|
|
while (1) {
|
|
/* sun5i sometimes gets stuck without this */
|
|
writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
|
|
}
|
|
#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
|
|
#if defined(CONFIG_MACH_SUN50I_H6)
|
|
/* WDOG is broken for some H6 rev. use the R_WDOG instead */
|
|
static const struct sunxi_wdog *wdog =
|
|
(struct sunxi_wdog *)SUNXI_R_WDOG_BASE;
|
|
#else
|
|
static const struct sunxi_wdog *wdog =
|
|
((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
|
|
#endif
|
|
/* Set the watchdog for its shortest interval (.5s) and wait */
|
|
writel(WDT_CFG_RESET, &wdog->cfg);
|
|
writel(WDT_MODE_EN, &wdog->mode);
|
|
writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
|
|
while (1) { }
|
|
#endif
|
|
}
|
|
#endif /* CONFIG_SYSRESET */
|
|
|
|
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && defined(CONFIG_CPU_V7A)
|
|
void enable_caches(void)
|
|
{
|
|
/* Enable D-cache. I-cache is already enabled in start.S */
|
|
dcache_enable();
|
|
}
|
|
#endif
|