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https://github.com/AsahiLinux/u-boot
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3a7ed5aa23
Current driver uses a Maximum value for MDIO_HOLD when doing 10G MDIO access, this is due to an errata A-006260 on T4 rev1.0 which is fixed on rev2.0, so remove the maximum value to use the default value for rev2.0. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
145 lines
3.7 KiB
C
145 lines
3.7 KiB
C
/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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* Andy Fleming <afleming@freescale.com>
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* Roy Zang <tie-fei.zang@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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* Some part is taken from tsec.c
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <phy.h>
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#include <asm/io.h>
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#include <asm/fsl_memac.h>
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#include <fm_eth.h>
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/*
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* Write value to the PHY for this device to the register at regnum, waiting
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* until the write is done before it returns. All PHY configuration has to be
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* done through the TSEC1 MIIM regs
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*/
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int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
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int regnum, u16 value)
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{
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u32 mdio_ctl;
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struct memac_mdio_controller *regs = bus->priv;
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u32 c45 = 1; /* Default to 10G interface */
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if (dev_addr == MDIO_DEVAD_NONE) {
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c45 = 0; /* clause 22 */
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dev_addr = regnum & 0x1f;
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clrbits_be32(®s->mdio_stat, MDIO_STAT_ENC);
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} else
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setbits_be32(®s->mdio_stat, MDIO_STAT_ENC);
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/* Wait till the bus is free */
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while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
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;
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/* Set the port and dev addr */
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mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
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out_be32(®s->mdio_ctl, mdio_ctl);
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/* Set the register address */
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if (c45)
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out_be32(®s->mdio_addr, regnum & 0xffff);
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/* Wait till the bus is free */
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while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
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;
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/* Write the value to the register */
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out_be32(®s->mdio_data, MDIO_DATA(value));
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/* Wait till the MDIO write is complete */
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while ((in_be32(®s->mdio_data)) & MDIO_DATA_BSY)
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;
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return 0;
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}
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/*
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* Reads from register regnum in the PHY for device dev, returning the value.
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* Clears miimcom first. All PHY configuration has to be done through the
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* TSEC1 MIIM regs
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*/
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int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
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int regnum)
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{
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u32 mdio_ctl;
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struct memac_mdio_controller *regs = bus->priv;
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u32 c45 = 1;
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if (dev_addr == MDIO_DEVAD_NONE) {
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c45 = 0; /* clause 22 */
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dev_addr = regnum & 0x1f;
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clrbits_be32(®s->mdio_stat, MDIO_STAT_ENC);
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} else
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setbits_be32(®s->mdio_stat, MDIO_STAT_ENC);
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/* Wait till the bus is free */
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while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
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;
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/* Set the Port and Device Addrs */
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mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
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out_be32(®s->mdio_ctl, mdio_ctl);
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/* Set the register address */
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if (c45)
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out_be32(®s->mdio_addr, regnum & 0xffff);
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/* Wait till the bus is free */
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while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
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;
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/* Initiate the read */
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mdio_ctl |= MDIO_CTL_READ;
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out_be32(®s->mdio_ctl, mdio_ctl);
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/* Wait till the MDIO write is complete */
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while ((in_be32(®s->mdio_data)) & MDIO_DATA_BSY)
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;
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/* Return all Fs if nothing was there */
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if (in_be32(®s->mdio_stat) & MDIO_STAT_RD_ER)
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return 0xffff;
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return in_be32(®s->mdio_data) & 0xffff;
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}
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int memac_mdio_reset(struct mii_dev *bus)
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{
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return 0;
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}
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int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info)
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{
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struct mii_dev *bus = mdio_alloc();
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if (!bus) {
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printf("Failed to allocate FM TGEC MDIO bus\n");
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return -1;
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}
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bus->read = memac_mdio_read;
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bus->write = memac_mdio_write;
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bus->reset = memac_mdio_reset;
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sprintf(bus->name, info->name);
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bus->priv = info->regs;
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/*
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* On some platforms like B4860, default value of MDIO_CLK_DIV bits
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* in mdio_stat(mdio_cfg) register generates MDIO clock too high
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* (much higher than 2.5MHz), violating the IEEE specs.
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* On other platforms like T1040, default value of MDIO_CLK_DIV bits
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* is zero, so MDIO clock is disabled.
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* So, for proper functioning of MDIO, MDIO_CLK_DIV bits needs to
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* be properly initialized.
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*/
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setbits_be32(&((struct memac_mdio_controller *)info->regs)->mdio_stat,
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MDIO_STAT_CLKDIV(258));
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return mdio_register(bus);
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}
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