mirror of
https://github.com/AsahiLinux/u-boot
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140 lines
3.6 KiB
C
140 lines
3.6 KiB
C
/*
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* (C) Copyright 2008-2011
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* Graeme Russ, <graeme.russ@gmail.com>
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*
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* (C) Copyright 2002
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* Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/io.h>
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#include <asm/pci.h>
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#include <asm/ic/pci.h>
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#include <asm/ic/sc520.h>
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static struct {
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u8 priority;
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u16 level_reg;
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u8 level_bit;
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} sc520_irq[] = {
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{ SC520_IRQ0, 0, 0x01 },
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{ SC520_IRQ1, 0, 0x02 },
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{ SC520_IRQ2, 1, 0x02 },
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{ SC520_IRQ3, 0, 0x08 },
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{ SC520_IRQ4, 0, 0x10 },
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{ SC520_IRQ5, 0, 0x20 },
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{ SC520_IRQ6, 0, 0x40 },
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{ SC520_IRQ7, 0, 0x80 },
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{ SC520_IRQ8, 1, 0x01 },
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{ SC520_IRQ9, 1, 0x02 },
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{ SC520_IRQ10, 1, 0x04 },
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{ SC520_IRQ11, 1, 0x08 },
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{ SC520_IRQ12, 1, 0x10 },
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{ SC520_IRQ13, 1, 0x20 },
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{ SC520_IRQ14, 1, 0x40 },
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{ SC520_IRQ15, 1, 0x80 }
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};
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/* The interrupt used for PCI INTA-INTD */
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int sc520_pci_ints[15] = {
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1
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};
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/* utility function to configure a pci interrupt */
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int pci_sc520_set_irq(int pci_pin, int irq)
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{
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int i;
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u8 tmpb;
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u16 tmpw;
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debug("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq);
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if (irq < 0 || irq > 15) {
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return -1; /* illegal irq */
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}
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if (pci_pin < 0 || pci_pin > 15) {
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return -1; /* illegal pci int pin */
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}
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/* first disable any non-pci interrupt source that use
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* this level */
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/* PCI interrupt mapping (A through D)*/
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for (i=0; i<=3 ;i++) {
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if (readb(&sc520_mmcr->pci_int_map[i]) == sc520_irq[irq].priority)
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writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[i]);
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}
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/* GP IRQ interrupt mapping */
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for (i=0; i<=10 ;i++) {
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if (readb(&sc520_mmcr->gp_int_map[i]) == sc520_irq[irq].priority)
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writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_int_map[i]);
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}
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/* Set the trigger to level */
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tmpb = readb(&sc520_mmcr->pic_mode[sc520_irq[irq].level_reg]);
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tmpb |= sc520_irq[irq].level_bit;
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writeb(tmpb, &sc520_mmcr->pic_mode[sc520_irq[irq].level_reg]);
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if (pci_pin < 4) {
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/* PCI INTA-INTD */
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/* route the interrupt */
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writeb(sc520_irq[irq].priority, &sc520_mmcr->pci_int_map[pci_pin]);
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} else {
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/* GPIRQ0-GPIRQ10 used for additional PCI INTS */
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writeb(sc520_irq[irq].priority, &sc520_mmcr->gp_int_map[pci_pin - 4]);
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/* also set the polarity in this case */
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tmpw = readw(&sc520_mmcr->intpinpol);
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tmpw |= (1 << (pci_pin-4));
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writew(tmpw, &sc520_mmcr->intpinpol);
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}
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/* register the pin */
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sc520_pci_ints[pci_pin] = irq;
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return 0; /* OK */
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}
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void pci_sc520_init(struct pci_controller *hose)
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{
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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hose->region_count = pci_set_regions(hose);
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pci_setup_type1(hose,
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SC520_REG_ADDR,
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SC520_REG_DATA);
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pci_register_hose(hose);
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hose->last_busno = pci_hose_scan(hose);
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/* enable target memory acceses on host brige */
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pci_write_config_word(0, PCI_COMMAND,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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}
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