mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-17 02:08:38 +00:00
b1aef0384f
As pointed by [1] and [2], commit
d64b9cdcd4 ("fdt: translate address if #size-cells = <0>") is wrong:
- It makes every 'reg' DT property translatable. It changes the address
translation so that for an I2C 'reg' address you'll get back as reg
the I2C controller address + reg value.
- The quirk must be fixed with platform code.
The clk_ti_get_reg_addr() is the platform code able to make the correct
address translation for the AM33xx clocks registers. Its implementation
was inspired by the Linux Kernel code.
[1] https://patchwork.ozlabs.org/project/uboot/patch/1614324949-61314-1-git-send-email-bmeng.cn@gmail.com/
[2] https://lore.kernel.org/linux-clk/20210402192054.7934-1-dariobin@libero.it/T/
Signed-off-by: Dario Binacchi <dariobin@libero.it>
120 lines
2.2 KiB
C
120 lines
2.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* TI clock utilities
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*
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* Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
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*/
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#include <common.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <regmap.h>
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#include <asm/io.h>
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#include <dm/device_compat.h>
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#include "clk.h"
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#define CLK_MAX_MEMMAPS 10
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struct clk_iomap {
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struct regmap *regmap;
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ofnode node;
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};
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static unsigned int clk_memmaps_num;
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static struct clk_iomap clk_memmaps[CLK_MAX_MEMMAPS];
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static void clk_ti_rmw(u32 val, u32 mask, fdt_addr_t reg)
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{
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u32 v;
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v = readl(reg);
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v &= ~mask;
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v |= val;
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writel(v, reg);
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}
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void clk_ti_latch(fdt_addr_t reg, s8 shift)
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{
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u32 latch;
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if (shift < 0)
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return;
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latch = 1 << shift;
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clk_ti_rmw(latch, latch, reg);
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clk_ti_rmw(0, latch, reg);
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readl(reg); /* OCP barrier */
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}
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void clk_ti_writel(u32 val, struct clk_ti_reg *reg)
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{
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struct clk_iomap *io = &clk_memmaps[reg->index];
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regmap_write(io->regmap, reg->offset, val);
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}
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u32 clk_ti_readl(struct clk_ti_reg *reg)
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{
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struct clk_iomap *io = &clk_memmaps[reg->index];
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u32 val;
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regmap_read(io->regmap, reg->offset, &val);
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return val;
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}
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static ofnode clk_ti_get_regmap_node(struct udevice *dev)
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{
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ofnode node = dev_ofnode(dev), parent;
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if (!ofnode_valid(node))
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return ofnode_null();
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parent = ofnode_get_parent(node);
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if (strcmp(ofnode_get_name(parent), "clocks"))
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return ofnode_null();
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return ofnode_get_parent(parent);
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}
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int clk_ti_get_reg_addr(struct udevice *dev, int index, struct clk_ti_reg *reg)
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{
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ofnode node;
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int i, ret;
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u32 val;
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ret = ofnode_read_u32_index(dev_ofnode(dev), "reg", index, &val);
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if (ret) {
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dev_err(dev, "%s must have reg[%d]\n", ofnode_get_name(node),
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index);
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return ret;
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}
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/* parent = ofnode_get_parent(parent); */
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node = clk_ti_get_regmap_node(dev);
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if (!ofnode_valid(node)) {
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dev_err(dev, "failed to get regmap node\n");
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return -EFAULT;
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}
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for (i = 0; i < clk_memmaps_num; i++) {
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if (ofnode_equal(clk_memmaps[i].node, node))
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break;
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}
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if (i == clk_memmaps_num) {
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if (i == CLK_MAX_MEMMAPS)
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return -ENOMEM;
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ret = regmap_init_mem(node, &clk_memmaps[i].regmap);
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if (ret)
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return ret;
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clk_memmaps[i].node = node;
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clk_memmaps_num++;
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}
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reg->index = i;
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reg->offset = val;
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return 0;
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}
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