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b19f57491a
Add driver for tegra SPI "SLINK" style driver. This controller is similar to the tegra20 SPI "SFLASH" controller. The difference is that the SLINK controller is a genernal purpose SPI controller and the SFLASH controller is special purpose and can only talk to FLASH devices. In addition there are potentially many instances of an SLINK controller on tegra and only a single instance of SFLASH. Tegra20 is currently ths only version of tegra that instantiates an SFLASH controller. This driver supports basic PIO mode of operation and is configurable (CONFIG_OF_CONTROL) to be driven off devicetree bindings. Up to 4 devices per controller may be attached, although typically only a single chip select line is exposed from tegra per controller so in reality this is usually limited to 1. To enable this driver, use CONFIG_TEGRA_SLINK Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
223 lines
4.8 KiB
C
223 lines
4.8 KiB
C
/*
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* (C) Copyright 2010,2011
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* NVIDIA Corporation <www.nvidia.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <ns16550.h>
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#include <linux/compiler.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#ifdef CONFIG_LCD
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#include <asm/arch/display.h>
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#endif
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#include <asm/arch/funcmux.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/pmu.h>
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#ifdef CONFIG_PWM_TEGRA
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#include <asm/arch/pwm.h>
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#endif
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#include <asm/arch/tegra.h>
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#include <asm/arch-tegra/board.h>
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#include <asm/arch-tegra/clk_rst.h>
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#include <asm/arch-tegra/pmc.h>
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#include <asm/arch-tegra/sys_proto.h>
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#include <asm/arch-tegra/uart.h>
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#include <asm/arch-tegra/warmboot.h>
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#ifdef CONFIG_TEGRA_CLOCK_SCALING
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#include <asm/arch/emc.h>
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#endif
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#ifdef CONFIG_USB_EHCI_TEGRA
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#include <asm/arch/usb.h>
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#endif
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#include <i2c.h>
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#include <spi.h>
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#include "emc.h"
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DECLARE_GLOBAL_DATA_PTR;
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const struct tegra_sysinfo sysinfo = {
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CONFIG_TEGRA_BOARD_STRING
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};
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#ifndef CONFIG_SPL_BUILD
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/*
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* Routine: timer_init
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* Description: init the timestamp and lastinc value
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*/
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int timer_init(void)
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{
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return 0;
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}
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#endif
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void __pin_mux_usb(void)
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{
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}
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void pin_mux_usb(void) __attribute__((weak, alias("__pin_mux_usb")));
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void __pin_mux_spi(void)
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{
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}
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void pin_mux_spi(void) __attribute__((weak, alias("__pin_mux_spi")));
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void __gpio_early_init_uart(void)
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{
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}
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void gpio_early_init_uart(void)
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__attribute__((weak, alias("__gpio_early_init_uart")));
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void __pin_mux_nand(void)
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{
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funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
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}
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void pin_mux_nand(void) __attribute__((weak, alias("__pin_mux_nand")));
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void __pin_mux_display(void)
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{
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}
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void pin_mux_display(void) __attribute__((weak, alias("__pin_mux_display")));
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/*
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* Routine: power_det_init
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* Description: turn off power detects
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*/
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static void power_det_init(void)
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{
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#if defined(CONFIG_TEGRA20)
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struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
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/* turn off power detects */
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writel(0, &pmc->pmc_pwr_det_latch);
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writel(0, &pmc->pmc_pwr_det);
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#endif
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}
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/*
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* Routine: board_init
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* Description: Early hardware init.
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*/
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int board_init(void)
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{
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__maybe_unused int err;
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/* Do clocks and UART first so that printf() works */
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clock_init();
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clock_verify();
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#ifdef CONFIG_SPI_UART_SWITCH
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gpio_config_uart();
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#endif
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#if defined(CONFIG_TEGRA_SPI) || defined(CONFIG_TEGRA_SLINK)
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pin_mux_spi();
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spi_init();
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#endif
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#ifdef CONFIG_PWM_TEGRA
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if (pwm_init(gd->fdt_blob))
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debug("%s: Failed to init pwm\n", __func__);
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#endif
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#ifdef CONFIG_LCD
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pin_mux_display();
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tegra_lcd_check_next_stage(gd->fdt_blob, 0);
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#endif
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/* boot param addr */
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gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
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power_det_init();
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#ifdef CONFIG_TEGRA_I2C
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#ifndef CONFIG_SYS_I2C_INIT_BOARD
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#error "You must define CONFIG_SYS_I2C_INIT_BOARD to use i2c on Nvidia boards"
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#endif
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i2c_init_board();
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# ifdef CONFIG_TEGRA_PMU
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if (pmu_set_nominal())
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debug("Failed to select nominal voltages\n");
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# ifdef CONFIG_TEGRA_CLOCK_SCALING
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err = board_emc_init();
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if (err)
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debug("Memory controller init failed: %d\n", err);
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# endif
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# endif /* CONFIG_TEGRA_PMU */
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#endif /* CONFIG_TEGRA_I2C */
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#ifdef CONFIG_USB_EHCI_TEGRA
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pin_mux_usb();
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board_usb_init(gd->fdt_blob);
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#endif
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#ifdef CONFIG_LCD
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tegra_lcd_check_next_stage(gd->fdt_blob, 0);
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#endif
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#ifdef CONFIG_TEGRA_NAND
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pin_mux_nand();
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#endif
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#ifdef CONFIG_TEGRA_LP0
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/* save Sdram params to PMC 2, 4, and 24 for WB0 */
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warmboot_save_sdram_params();
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/* prepare the WB code to LP0 location */
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warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
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#endif
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return 0;
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}
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#ifdef CONFIG_BOARD_EARLY_INIT_F
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static void __gpio_early_init(void)
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{
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}
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void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init")));
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int board_early_init_f(void)
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{
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#if defined(CONFIG_TEGRA30)
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pinmux_init();
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#endif
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board_init_uart_f();
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/* Initialize periph GPIOs */
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gpio_early_init();
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gpio_early_init_uart();
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#ifdef CONFIG_LCD
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tegra_lcd_early_init(gd->fdt_blob);
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#endif
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return 0;
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}
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#endif /* EARLY_INIT */
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int board_late_init(void)
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{
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#ifdef CONFIG_LCD
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/* Make sure we finish initing the LCD */
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tegra_lcd_check_next_stage(gd->fdt_blob, 1);
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#endif
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return 0;
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}
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